Vertical gallium nitride transistors and methods of fabricating the same
A vertical gallium nitride transistor according to an exemplary embodiment of the present invention includes a semiconductor structure including a first semiconductor layer of a first conductivity-type having a first surface and sidewalls, a second semiconductor layer of the first conductivity-type surrounding the first surface and the sidewalls of the first semiconductor layer, and a third semiconductor layer of a second conductivity-type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other.
1. A vertical gallium nitride transistor, comprising:
a first semiconductor layer of a first conductivity type comprising a first surface, a second surface opposite to the first surface, and sidewalls;
a second semiconductor layer of the first conductivity type surrounding the second surface and the sidewalls of the first semiconductor layer;
a third semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other;
a source electrode disposed on the first surface of the first semiconductor layer, the source electrode being electrically connected to the first semiconductor layer;
a gate electrode disposed on a first surface of the third semiconductor layer between the first and second semiconductor layers;
a drain electrode, wherein the second semiconductor layer is disposed on a first surface of the drain electrode; and
a current blocking layer disposed between the drain electrode and the second semiconductor layer, the current blocking layer comprising a lower surface in direct contact with the drain electrode and an upper surface that is in direct contact with the second semiconductor layer,
wherein the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer comprise a semiconductor structure.
2. The vertical gallium nitride transistor of claim 1 , wherein the semiconductor structure further comprises a doped layer disposed between the drain electrode and the second semiconductor layer.
3. The vertical gallium nitride transistor of claim 1 , further comprising a support substrate, wherein a second surface of the drain electrode opposite to the first surface is disposed on the support substrate.
4. The vertical gallium nitride transistor of claim 1 , further comprising a current blocking layer disposed between the drain electrode and the second semiconductor layer.
5. The vertical gallium nitride transistor of claim 1 ,
wherein the first and second semiconductor layers comprise N-type gallium nitride; and
wherein the third semiconductor layer comprises P-type gallium nitride.
6. The vertical gallium nitride transistor of claim 1 , wherein:
the third semiconductor layer comprises a plurality of third semiconductor layers;
the first semiconductor layer comprises a plurality of first semiconductor layers, the plurality of first semiconductor layers comprising a stripe pattern and a lower first semiconductor layer covering sidewalls and a bottom surface of the strip pattern;
the source electrode comprises a plurality of source electrodes;
each of the plurality of third semiconductor layers surround at least two of the first semiconductor layers;
each of the source electrodes is electrically connected to at least two of the first semiconductor layers; and
the second semiconductor layer surrounds the sidewalls and a bottom surface of the lower first semiconductor layer.
7. The vertical gallium nitride transistor of claim 1 ,
wherein the drain electrode contacts the second semiconductor layer, between each of the current blocking layers.
8. The vertical gallium nitride transistor of claim 7 , further comprising a low resistive layer disposed between the drain electrode and the second semiconductor layer, the low resistive layer being an etch damage layer formed by etching a portion of the second semiconductor layer.