Semiconductor memory device

1. A semiconductor memory device comprising:

a memory cell array in which memory cells arranged at positions where bit lines and word lines cross each other are arranged on a semiconductor substrate;

a sense amplifier configured to read data stored in one of the memory cells via the bit line in a read operation;

a hookup region comprising a transfer transistor arranged between the memory cell array and the sense amplifier, one end of a current path of the transfer transistor being connected to a first interconnect formed between the semiconductor substrate and the bit line, the other end of the current path of the transfer transistor being connected to the sense amplifier;

a guard ring region arranged between the memory cell array and the hookup region and enclosing the memory cell array, the guard ring region including a cell guard ring providing potential to the semiconductor substrate;

a first contact plug arranged to overlap the guard ring region, the first contact plug electrically connecting the bit line to the first interconnect;

a second interconnect formed between the semiconductor substrate and the first interconnect in the guard ring region, the second interconnect providing the potential to the cell guard ring;

a third interconnect arranged in a same interconnect layer as the first interconnect and having the potential provided to the cell guard ring; and

a second contact plug arranged between the second interconnect and the third interconnect and electrically connecting the second interconnect and the third interconnect.

2. The semiconductor memory device according to claim 1 , further comprising a third contact plug arranged between the cell guard ring and the third interconnect, the third contact plug electrically connecting the cell guard ring and the third interconnect.

3. The semiconductor memory device according to claim 1 , wherein the cell guard ring includes an active area of the semiconductor substrate.

4. The semiconductor memory device according to claim 1 , wherein an electric resistance of the second interconnect is equal to or less than an electric resistance of the first interconnect.

5. The semiconductor memory device according to claim 1 , wherein the memory cell array includes a NAND cell unit.

6. The semiconductor memory device according to claim 5 , wherein the NAND cell unit includes the memory cells connected in series and first, second select gate transistors connected to sandwich the memory cells.

7. The semiconductor memory device according to claim 6 , wherein one end of the NAND cell unit is connected to the bit line via the first select gate transistor.

8. The semiconductor memory device according to claim 6 , wherein the second interconnect is formed in a same interconnect layer as the gate electrode of one of the memory cells.

9. The semiconductor memory device according to claim 1 , wherein the sense amplifier includes a low withstand voltage transistor, and the transfer transistor includes a high withstand voltage transistor having a withstand voltage which is higher than a withstand voltage of the low withstand voltage transistor.

10. A semiconductor memory device comprising:

a memory cell array in which memory cells each connected to a bit line and a word line are arranged on a semiconductor substrate;

a sense amplifier configured to read data stored in one of the memory cells via the bit line in a read operation;

a hookup region comprising a transfer transistor arranged between the memory cell array and the sense amplifier, one end of a current path of the transfer transistor being connected to a first interconnect formed between the semiconductor substrate and the bit line, the other end of the current path of the transfer transistor being connected to the sense amplifier;

a guard ring region arranged between the memory cell array and the hookup region and enclosing the memory cell array, the guard ring region including a cell guard ring providing potential to the semiconductor substrate;

a second interconnect formed in a same interconnect layer as the first interconnect on the memory cell array;

a third interconnect formed in a same interconnect layer as the first interconnect on the guard ring region and providing the potential to the cell guard ring, wherein a width of the third interconnect is narrower than a width of the second interconnect but is wider than a width of the first interconnect;

a fourth interconnect formed between the semiconductor substrate and the first interconnect in the guard ring region, the fourth interconnect providing the potential to the cell guard ring; and

a first contact plug arranged between the third interconnect and the fourth interconnect and electrically connecting the third interconnect and the fourth interconnect.

11. The semiconductor memory device according to claim 10 , further comprising a second contact plug arranged between the cell guard ring and the third interconnect and electrically connecting the cell guard ring and the third interconnect.

12. The semiconductor memory device according to claim 11 , further comprising a third contact plug arranged to overlap the guard ring region and electrically connecting the bit line to the first interconnect.

13. The semiconductor memory device according to claim 10 , wherein the cell guard ring includes an active area of the semiconductor substrate.

14. The semiconductor memory device according to claim 10 , wherein an electric resistance of the fourth interconnect is equal to or less than an electric resistance of the first interconnect.

15. The semiconductor memory device according to claim 10 , wherein the memory cell array includes a NAND cell unit.

16. The semiconductor memory device according to claim 15 , wherein the NAND cell unit includes the memory cells connected in series and first, second select gate transistors connected to sandwich the memory cells.

17. The semiconductor memory device according to claim 16 , wherein one end of the NAND cell unit is connected to the bit line via the first select gate transistor.

18. The semiconductor memory device according to claim 10 , wherein the fourth interconnect is formed in a same interconnect layer as the gate electrode of one of the memory cells.