IP Library Granted Patent US 9,224,619
Granted Patent B2
US 9,224,619 · App. 14/502,345 · Granted Dec 29, 2015

Semiconductor device and fabricating method thereof

Inventors: Seol-Min Yi (Seoul, KR); Dae-Hyun Moon (Gyeonggi-do, KR); Joon-Seok Moon (Seoul, KR); Se-Keun Park (Gyeonggi-do, KR); Hyeoung-Won Seo (Gyeonggi-do, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L21/32133H01L27/10814H01L27/10823H01L27/10876H01L27/228H01L29/4236H01L29/42376H01L21/28088H01L29/4966
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Quick Facts
Patent No.
US 9,224,619
App. No.
14/502,345
Granted
Dec 29, 2015
Kind
B2
Abstract

The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.

Claims (26)

1. A semiconductor device comprising:

a substrate;

a trench formed in the substrate;

a gate insulation layer conformally formed on the inner surface of the trench;

a buried gate electrode formed on the gate insulation layer and filling a portion of the trench; and

a capping layer formed on the buried gate electrodes and filling the trench,

wherein the buried gate electrode includes a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.

2. The semiconductor device of claim 1 , wherein the capping layer is formed on the first gate electrode and the air gap.

3. The semiconductor device of claim 1 , wherein the air gap is surrounded by the first gate electrode, the second gate electrode, the gate insulation layer and the capping layer.

4. The semiconductor device of claim 1 , wherein the second gate electrode surrounds sidewalls of the bottom portion of the first gate electrode and a bottom surface of the first gate electrode.

5. The semiconductor device of claim 1 , wherein the air gap is formed at opposite sides of the first gate electrode.

6. The semiconductor device of claim 1 , wherein the first gate electrode includes tungsten (W).

7. The semiconductor device of claim 1 , wherein the second gate electrode includes titanium nitride (TiN) or tungsten nitride (WN).

8. The semiconductor device of claim 1 , wherein the capping layer includes silicon nitride (SiN).

9. The semiconductor device of claim 1 , wherein the air gap is surrounded by the first gate electrode, the second gate electrode, the gate insulation layer and the capping layer.

10. The semiconductor device of claim 1 , wherein the second gate electrode surrounds sidewalls of the bottom portion of the first gate electrode and a bottom surface of the first gate electrode.

11. A semiconductor device including a switch transistor comprising;

a substrate;

a trench formed in the substrate;

a gate insulation layer conformally formed on the inner surface of the trench;

a buried gate electrode formed on the gate insulation layer and filling a portion of the trench;

a capping layer formed on the buried gate electrodes and filling the trench; and

a source/drain formed in the substrate adjacent to the buried gate electrode;

wherein the buried gate electrode includes a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.

12. The semiconductor device of claim 11 , further comprising a capacitor or a magnetic tunnel junction connected to the switch transistor.

13. The semiconductor device of claim 11 , wherein the capping layer is formed on the first gate electrode and the air gap.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2014
From: YI, SEOL-MIN; MOON, DAE-HYUN; MOON, JOON-SEOK; PARK, SE-KEUN; SEO, HYEOUNG-WON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 033854/0484 →
Priority Claims (1)
KR 10-2014-0012616 · Feb 4, 2014 · national
Continuity (1)
Related Publication 20150221742A1 · Aug 6, 2015