Multiple thickness gate dielectrics for replacement gate field effect transistors
After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.
1. A method of forming a semiconductor structure comprising:
providing gate cavities surrounded by a planarization dielectric layer over a semiconductor substrate, wherein a top surface of a semiconductor oxide-based dielectric portion is physically exposed at a bottom of each of said gate cavities;
depositing a silicon oxide layer on each of said semiconductor oxide-based dielectric portions;
nitridating at least a portion of said silicon oxide layer to form a silicon oxynitride layer;
physically exposing a surface of said semiconductor substrate within a gate cavity among said gate cavities, while preventing removal of said silicon oxynitride layer in another gate cavity among said gate cavities;
forming a high dielectric constant (high-k) gate dielectric layer in said gate cavity and said another gate cavity; and
filling said gate cavity and said another gate cavity with a conductive material.
2. The method of claim 1 , wherein said silicon oxide layer is formed by atomic layer deposition of silicon atoms and oxygen atoms.
3. The method of claim 2 , wherein said silicon oxide layer is formed on said semiconductor oxide-based dielectric portions and on sidewalls of said gate cavities.
4. The method of claim 1 , further comprising:
forming disposable gate structures on said semiconductor substrate, each of said disposable gate structures comprising one of said semiconductor oxide-based gate dielectric portions and a disposable gate material portion;
forming said planarization dielectric layer over said semiconductor substrate and around said disposable gate structures; and
forming said gate cavities by removing said disposable gate material portions selective to said silicon oxide-based gate dielectric portions.
5. The method of claim 4 , wherein said semiconductor oxide-based gate dielectric portions are formed by:
forming a semiconductor oxide-based gate dielectric layer; and
patterning said semiconductor oxide-based gate dielectric layer into said semiconductor oxide-based gate dielectric portions.
6. The method of claim 4 , further comprising removing said disposable gate material portions selective to said semiconductor oxide-based gate dielectric portions, wherein volume from which said disposable gate material portions constitute said gate cavities.
7. The method of claim 1 , further comprising:
depositing a metallic nitride layer on said silicon oxide layer; and
patterning said metallic nitride layer, wherein a remaining portion of said metallic nitride layer is present in said gate cavity and is not present in said another gate cavity.
8. The method of claim 7 , wherein said metallic nitride layer prevents nitridation of portions of said silicon oxide layer underneath said metallic nitride layer during said nitridating.
9. The method of claim 8 , wherein said high-k gate dielectric layer is formed directly on a nitridated portion of said silicon oxide layer and on a portion of said silicon oxide layer that is not nitridated.
10. The method of claim 7 , wherein a remaining portion of said metallic nitride layer is present in yet another gate cavity among said gate cavities after patterning said metallic nitride layer, and said method further comprises removing a portion of said silicon oxide layer after said nitridating while a masking material layer overlies said silicon oxynitride layer in said yet another gate cavity.