Mitigating reliability degradation of analog memory cells during long static and erased state retention
A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
1. A method, comprising:
in a non-volatile memory that includes multiple memory cells that store data using a predefined set of programming levels, including an erased level, wherein each programming level of the predefined set of programming levels corresponds to at least one data value, receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period;
programming the memory cells in the group to a retention programming level that is different from each of the predefined set of programming levels; and
upon preparing to program the group of memory cells with data, erasing the group of memory cells to the erased level and then programming the data in the group of memory cells.
2. The method according to claim 1 , wherein the retention programming level is higher than each of the programming levels in the predefined set of programming levels.
3. The method according to claim 1 , wherein setting the memory cells to the retention programming level comprises retaining the group of memory cells at their present programming levels.
4. The method according to claim 1 , further comprising managing a retention pool of memory cell blocks that are programmed to the retention programming level, and, upon receiving the data for storage, selecting the group of memory cells from the memory cell blocks in the retention pool.
5. The method according to claim 4 , further comprising managing an erased pool of memory cell blocks whose cells are erased to the erased level, and wherein selecting the group of memory cells comprises selecting a block from the erased pool when available.
6. An apparatus for data storage, comprising:
a non-volatile memory that includes multiple memory cells that store data using a predefined set of programming levels, including an erased level, wherein each programming level of the predefined set of programming levels corresponds to at least one data value; and
storage circuitry configured to:
receive a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period;
program the memory cells in the group to a retention programming level that is different from each of the predefined set of programming levels; and
upon preparing to program the group of memory cells with data, erase the group of memory cells to the erased level and program the data in the group of memory cells.
7. The apparatus according to claim 6 , wherein the retention programming level is higher than each of the programming levels in the predefined set of programming levels.
8. The apparatus according to claim 6 , wherein the storage circuitry is further configured to set the memory cells to the retention programming level by retaining the group of memory cells at their present programming levels.
9. The apparatus according to claim 6 , wherein the storage circuitry is further configured to manage a retention pool of memory cell blocks that are programmed to the retention programming level, and, upon receiving the data for storage, to select the group of memory cells from the memory cell blocks in the retention pool.
10. The apparatus according to claim 9 , wherein the storage circuitry is further configured to manage an erased pool of memory cell blocks whose cells are erased to the erased level, and to select the group of memory cells by selecting a block from the erased pool when available.
11. A method, comprising:
in a non-volatile memory that includes multiple memory cells, receiving a storage operation to store new data in the memory cells;
upon detecting that the memory cells have been retained in an erased level for a duration longer than a predefined time period, performing a preliminary storage operation on the memory cells; and
programming the new data in the memory cells upon completion of the preliminary storage operation.
12. The method according to claim 11 , wherein receiving the storage operation comprises receiving a programming operation with data for storage, wherein performing the preliminary storage operation comprises applying one or more dummy erasure and program (E/P) cycles to the memory cells, and wherein applying the storage operation comprises programming the received data to the memory cells.
13. The method according to claim 11 , wherein receiving the storage operation comprises receiving an erasure operation, wherein performing the preliminary storage operation comprises programming at least some of the memory cells to a predefined level, and wherein applying the storage operation comprises erasing the memory cells.
14. The method according to claim 11 , wherein receiving the storage operation comprises receiving a programming operation with data for storage, wherein performing the preliminary storage operation comprises programming a group of the memory cells to a predefined level, and wherein applying the storage operation comprises programming the received data to the group of memory cells.
15. An apparatus for data storage, comprising:
a non-volatile memory, including multiple memory cells; and
storage circuitry configured to:
receive a storage operation to store new data in the memory cells;
upon detecting that the memory cells have been retained in an erased level for a duration longer than a predefined time period, perform a preliminary storage operation on the memory cells; and
program the new data in the memory cells upon completion of the preliminary storage operation.
16. The apparatus according to claim 15 , wherein the storage circuitry is further configured to receive a programming operation with data for storage, to perform the preliminary storage operation by applying one or more dummy erasure and program (E/P) cycles to the memory cells, and to program the received data to the memory cells.
17. The apparatus according to claim 15 , wherein the storage circuitry is further configured to receive an erasure operation, to perform the preliminary storage operation by programming at least some of the memory cells to a predefined level, and to apply the storage operation by erasing the memory cells.
18. The apparatus according to claim 15 , wherein the storage circuitry is further configured to receive a programming operation with data for storage, to perform the preliminary storage operation by programming a group of the memory cells to a predefined level, and to apply the storage operation by programming the received data to the group of memory cells.