Integrated circuit having improved radiation immunity
An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.
1. An integrated circuit having improved radiation immunity, the integrated circuit comprising:
a substrate;
a P-well formed on the substrate and having N-type transistors of a memory cell; and
an N-well formed on the substrate and having P-type transistors of the memory cell;
wherein the integrated circuit further comprising a first P-tap between the N-well and the N-type transistors in the P-well;
wherein the memory cell is a 12 transistor memory cell; and
wherein the memory cell has a first pair of nodes and a second pair of nodes, and N-well regions forming an N-type transistor associated with the second pair of nodes are located between P-well regions forming a P-type transistor associated with a node of the first pair of nodes and N-well regions forming an N-type transistor associated with another node of the first pair of nodes.
2. The integrated circuit of claim 1 , further comprising a word line contact located outside an area defined by the N-well.
3. The integrated circuit of claim 1 , wherein a power trace is located outside an area defined by the N-well.
4. The integrated circuit of claim 1 , further comprising a second P-tap on a second side of the N-well opposite the first side of the N-well.
5. The integrated circuit of claim 4 , wherein the 12 transistor memory; cell comprise N-type transistors on the first side of the N-well and on the second side of the N-well, the integrated circuit further comprising a first word line contact associated with N-type transistors on the first side of the N-well and a second word line contact associated with N-type transistors on the second side of the N-well.
6. The integrated circuit of claim 4 , wherein a power trace is located outside an area occupied by the N-well.
7. An integrated circuit having improved radiation immunity, the integrated circuit comprising:
a substrate;
a P-well formed on the substrate and having N-type transistors of a memory cell; and
an N-well formed on the substrate and having P-type transistors of the memory cell;
wherein the memory cell has a first pair of nodes and a second pair of nodes, and N-well regions forming an N-type transistor associated with the second pair of nodes are located between P-well regions forming a P-type transistor associated with a node of the first pair of nodes and N-well regions forming an N-type transistor associated with another node of the first pair of nodes.
8. The integrated circuit of claim 7 , further comprising a first P-tap on a first side of the N-well and a second P-tap on a second side of the N-well.
9. The integrated circuit of claim 8 , wherein the memory cell is a 12 transistor memory cell and comprises N-type transistors on the first side of the N-well and on the second side of the N-well, the integrated circuit further comprising a first word line contact associated with N-type transistors on the first side of the N-well and a second word line contact associated with N-type transistors on the second side of the N-well.
10. The integrated circuit of claim 7 , wherein the P-type transistors are positioned within the N-well to increase the distance between the node of the first pair of nodes and the other node of the first pair of nodes.
11. A method of forming an integrated circuit having improved radiation immunity, the method comprising:
providing a substrate;
forming a P-well on the substrate, the P-well having N-type transistors of a memory cell; and
forming an N-well on the substrate, the N-well having P-type transistors of the memory cell;
wherein the memory cell has a first pair of nodes and a second pair of nodes, and N-well regions forming an N-type transistor associated with the second pair of nodes are located between P-well regions forming a P-type transistor associated with a node of the first pair of nodes and N-well regions forming an N-type transistor associated with another node of the first pair of nodes.
12. The method of claim 11 , further comprising a word line contact located outside an area defined by the N-well.
13. The method of claim 11 , wherein forming the N-well and the P-well of the memory cell comprises forming a 6 transistor memory cell having a P-tap between the N-well and the N-type transistors in the P-well.
14. The method of claim 11 , further comprising forming a power trace outside an area defined by the N-well.
15. The method of claim 11 , wherein forming the N-well and P-well of the memory cell comprises forming a 12 transistor memory cell comprising a first P-tap on a first side of the N-well and a second P-tap on a second side of the N-well opposite the first side of the N-well.
16. The method of claim 15 , wherein forming the 12 transistor memory cell comprises forming N-type transistors on the first side of the N-well and on the second side of the N-well, and further comprising forming a first word line contact on the first side of the N-well and a second word line contact on the second side of the N-well.
17. The method of claim 15 , further comprising forming a power trace that is located outside an area defined by the N-well.