IP Library › Granted Patent US 9,245,921
Granted Patent B2
US 9,245,921 · App. 14/537,633 · Granted Jan 26, 2016

Semiconductor device including image pick up device

Inventors: Yuki Yamamoto (Kanagawa, JP); Yukio Nishida (Kanagawa, JP); Tomohiro Yamashita (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
H01L27/14812H01L27/14609H01L27/14614H01L27/14641H01L27/14887H01L27/10876H01L27/14831H01L29/1091H01L29/42396
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Quick Facts
Patent No.
US 9,245,921
App. No.
14/537,633
Granted
Jan 26, 2016
Kind
B2
Abstract

The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part.

Claims (20)

1. A semiconductor device comprising:

a photoelectric conversion element that generates a signal electric charge in accordance with a light amount of incident light;

a forwarding transistor that forwards the signal electric charge to a charge detector;

an amplification transistor that outputs an electric signal corresponding to a potential variation in the charge detector;

a resetting transistor that resets a potential of the charge detector to a predetermined value; and

a selection transistor that externally outputs the electric signal the amplification transistor outputs,

wherein a first gate electrode of the amplification transistor and a second gate electrode of the selection transistor, which cross over an active region surrounded by an element isolation region, are formed in the active region, and

wherein in a portion immediately above the active region, a gate length of at least one end portion in a gate width direction of the first gate electrode is larger than that of a central portion in the gate width direction of the first gate electrode.

2. The semiconductor device according to claim 1 ,

wherein the first gate electrode has a structure in which a plurality of third electrodes arrayed in the gate width direction are coupled in parallel with each other.

3. The semiconductor device according to claim 1 ,

wherein in a portion immediately above the active region, a gate length of each of both end portions in the gate width direction of the first gate electrode is larger than that of a central portion in the gate width direction of the first gate electrode.

4. The semiconductor device according to claim 1 ,

wherein in a portion immediately below the first gate electrode, a diffusion layer, having the same conductive type as that of a channel region of the amplification transistor, is formed in the active region adjacent to the element isolation region.

5. The semiconductor device according to claim 4 ,

wherein in a portion immediately below the second gate electrode, a diffusion layer, having the same conductive type as that of a channel region of the selection transistor, is formed in the active region adjacent to the element isolation region.

6. The semiconductor device according to claim 5 ,

wherein the resetting transistor, the forwarding transistor, and the photoelectric conversion element do not include the diffusion layer.

7. The semiconductor device according to claim 1 ,

wherein the amplification transistor is arranged to be sandwiched by a plurality of photodiodes in the gate width direction of the first gate electrode.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TYPOGRAPHICAL ERROR IN THIRD ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 034139 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 16, 2015
From: YAMAMOTO, YUKI; NISHIDA, YUKIO; YAMASHITA, TOMOHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 035271/0579 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: YAMAMOTO, YUKI; NISHIDA, YUKIO; YAMASJOTA, TOMOHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 034139/0807 →
Priority Claims (1)
JP 2014-009003 · Jan 21, 2014 · national
Continuity (1)
Related Publication 20150206920A1 · Jul 23, 2015