IP Library Granted Patent US 9,256,439
Granted Patent B2
US 9,256,439 · App. 13/443,465 · Granted Feb 9, 2016

Parallel processing of two-dimensional data, storage of plural data of the processing results in a cache line and transfer of the data to a memory as in the cache line

Inventor: Hirokazu Takahashi (Tokyo, JP)
Assignee: Canon Kabushiki Kaisha
G06F9/3885G06F9/345G06F12/0284G06F12/0842G06F12/0886G06T1/60G06F12/0875G06F2212/1016G06F2212/455
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Quick Facts
Patent No.
US 9,256,439
App. No.
13/443,465
Granted
Feb 9, 2016
Kind
B2
Abstract

A data processing apparatus causes multiple processors to process in parallel input data that is arrayed two-dimensionally, and stores the data of the processing results in a cache line of a cache memory, where the data of the processing results includes a plurality of pieces of data of a predetermined width that is smaller than a cache line width of the cache memory. The data stored in the cache memory is then transferred together to a main memory as in the cache line.

Claims (12)

1. A data processing apparatus comprising:

a plurality of processing units that process, in parallel and in units of a predetermined width, input data that is arranged in two-dimensional array form, which input data is read out from a main memory, wherein (a) each of the processing units has a cache memory, (b) the predetermined width is the width of one direction of a two-dimensional array to be processed by each of the plurality of processing units, and (c) the predetermined width is smaller than a cache line width of the cache memory; and

a control unit that stores in a cache line of the cache memory, in accordance with the cache line width of the processing unit, data of the processing results of the processing unit, wherein the data of the processing results includes a plurality of pieces of data of the predetermined width,

wherein, for each of the plurality of processing units, the control unit transfers, to the main memory, the data of the processing results stored in the respective cache memory of the processing unit, such that the data of the processing results is transferred together as in the cache line of the respective cache memory.

2. The apparatus according to claim 1 , further comprising a data processing unit that reads out the data of processing results stored in the main memory and carries out a second data process on the read-out data of processing results.

3. The apparatus according to claim 2 , wherein the data processing unit reads out the data of processing results stored in the storage unit line-by-line.

4. The apparatus according to claim 2 , wherein the data processing unit reads out two-dimensional data of processing results from the storage unit in units each having a particular two-dimensional size.

5. The apparatus according to claim 1 , wherein the input data is stored in a first area of the main memory, and the data of processing results is stored in a second area of the main memory.

6. The apparatus according to claim 1 , wherein the predetermined width is less than or equal to half the cache line width.

7. A data processing method performed by a data processing apparatus comprising a plurality of processing units that process, in parallel and in units of a predetermined width, input data that is arrayed two-dimensionally, the input data being read out from a main memory, wherein (a) each of the processing units has a cache memory, (b) the predetermined width is the width of one direction of a two-dimensional array to be processed by each of the plurality of processing units, and (c) the predetermined width is smaller than a cache line width of the cache memory, the method comprising:

storing in a cache line of the cache memory, in accordance with the cache line width of the processing unit, data of the processing results of the processing unit, wherein the data of the processing results includes a plurality of pieces of data of the predetermined width; and

transferring to the main memory, for each of the plurality of processing units, the data of the processing results stored in the respective cache memory of the processing unit, such that the data of the processing results is transferred together as in the cache line of the respective cache memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2012
From: TAKAHASHI, HIROKAZU
To: CANON KABUSHIKI KAISHA
Reel/Frame 028761/0707 →
Priority Claims (1)
JP 2011-108733 · May 13, 2011 · national
Continuity (1)
Related Publication 20120290815A1 · Nov 15, 2012