IP Library › Granted Patent US 9,257,509
Granted Patent B2
US 9,257,509 · App. 13/996,214 · Granted Feb 9, 2016

Electrical devices with graphene on boron nitride

Inventors: Kenneth Shepard (Ossining, NY); Philip Kim (New York, NY); James C. Hone (New York, NY); Cory Dean (New York, NY)
Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
H01L29/1606H01L29/0665H01L29/518H01L29/66742H01L29/778H01L29/78603H01L29/78684
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Quick Facts
Patent No.
US 9,257,509
App. No.
13/996,214
Granted
Feb 9, 2016
Kind
B2
Abstract

Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (GFETs) including boron nitride.

Claims (14)

1. A method of forming a graphene field effect transistor comprising:

forming a graphene layer using chemical vapor deposition techniques;

mechanically placing the graphene layer on a boron nitride layer, wherein the graphene layer is placed with a non-zero degree of lattice mismatch with the boron nitride layer to reduce a bandgap effect during operation of the transistor;

forming a pair of source/drain regions coupled to the graphene layer, defining a graphene channel region located therebetween; and

coupling a gate electrode adjacent to the graphene channel region, and electrically separated from the graphene channel region.

2. The method of claim 1 , wherein the forming the graphene layer using chemical vapor deposition techniques includes forming the graphene layer using a sacrificial catalyst layer.

3. The method of claim 2 , wherein the forming the graphene layer using a sacrificial catalyst layer includes forming the graphene layer using a metallic catalyst layer.

4. A method of forming a graphene field effect transistor comprising:

forming a pair of source/drain regions on a graphene layer, defining a graphene channel region located therebetween;

forming a boron nitride layer using chemical vapor deposition techniques;

mechanically placing the boron nitride layer on the graphene layer, forming an interface having a non-zero degree of lattice mismatch with the graphene channel region to reduce a bandgap effect during operation of the transistor; and

coupling a gate electrode adjacent to the graphene channel region, and electrically separated from the graphene channel region.

5. The method of claim 4 , wherein the forming the boron nitride layer using chemical vapor deposition techniques includes forming the boron nitride layer using a sacrificial catalyst layer.

6. The method of claim 5 , wherein the forming the boron nitride layer using a sacrificial catalyst layer includes forming the boron nitride layer using a metallic catalyst layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2015
From: SHEPARD, KENNETH; KIM, PHILIP; HONE, JAMES C.; DEAN, CORY
To: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
Reel/Frame 036570/0845 →
Continuity (2)
Provisional Application 61425636 · Dec 21, 2010
Related Publication 20140299839A1 · Oct 9, 2014