Amplifier circuit and wireless communication equipment
Distortion compensation is performed taking into account a memory effect that occurs in a signal path other than an input-to-output path of an amplifier. An amplifier circuit 1 includes an amplifier 2 that amplifies a signal, a variable power supply 3 that varies a power supply voltage of the amplifier 2 in accordance with envelope change, and a distortion compensation section 4 that performs compensation for distortion characteristics. The distortion compensation section 4 performs the distortion compensation, based on an amplifier model which represents a memory effect that occurs on a path from a signal input port 2 a of the amplifier 2 to a signal output port 2 b thereof, and a memory effect that occurs on a path from a power supply port 2 c of the amplifier 2 to the signal output port 2 b thereof.
1. An amplifier circuit, comprising:
an amplifier that amplifies a signal;
a variable power supply that varies a power supply voltage or a power supply current to be supplied to a power supply port of the amplifier, in accordance with change in an envelope of the signal; and
a distortion compensation section that performs compensation for distortion characteristics of the amplifier, wherein
the distortion compensation section performs a process of compensating a memory effect that occurs on a path from the power supply port to a signal output port,
the distortion compensation section includes an estimation section that estimates a model of the amplifier, and performs distortion compensation based on the model estimated by the estimation section,
the model represents at least the memory effect that occurs on the path from the power supply port to the signal output port, and
the process is performed on the signal to be inputted to a signal input port of the amplifier.
2. The amplifier circuit according to claim 1 , wherein
the distortion compensation section performs a process of compensating a second memory effect that occurs on a path from a signal input port of the amplifier to the signal output port.
3. The amplifier circuit according to claim 1 , wherein
in the model, the amplifier is modeled as a combination of a plurality of element amplifiers,
the plurality of element amplifiers in the model are each given an input signal inputted to the signal input port, and the power supply voltage or the power supply current supplied from the variable power supply,
a combination of outputs from the plurality of element amplifiers in the model corresponds to an output of the amplifier,
the plurality of element amplifiers in the model each have nonlinear characteristic which is defined based on the input signal inputted to the signal input port, and the power supply voltage or the power supply current supplied from the variable power supply, and
the plurality of element amplifiers in the model are given the power supply voltage or the power supply current at different times, respectively.
4. The amplifier circuit according to claim 3 , wherein
the plurality of element amplifiers in the model are each modeled as a combination of a plurality of nonlinear elements,
the plurality of nonlinear elements are each given the input signal inputted to the signal input port,
a combination of outputs of the plurality of nonlinear elements corresponds to an output of the element amplifier,
the plurality of nonlinear elements each have nonlinear characteristic which is defined based on the input signal and the power supply voltage or the power supply current, and
the plurality of nonlinear elements are given the input signal at different times, respectively.
5. The amplifier circuit according to claim 1 , wherein
the model is an amplifier model based on the following equation:
y
[
n
]
=
∑
l
=
-
L
1
L
2
∑
m
=
-
M
1
M
2
∑
k
=
1
K
m
,
l
H
k
,
l
,
m
V
[
n
-
l
-
m
]
k
-
1
·
u
[
n
-
l
]
where
y[n] is an output of the amplifier at a time instance n, n being an integer,
k is an order,
l is a relative delay that occurs with respect to an input signal u[n] of the amplifier, in a path (hereinafter referred to as a “signal amplification path”) from a signal input port of the amplifier to a signal output port,
m is a relative delay that occurs with respect to the input signal u[n] of the amplifier, in a path (hereinafter referred to as a “power supply path”) from the power supply port of the amplifier to the signal output port,
L 1 is a maximum value of relative number of preceding samples in the signal amplification path,
L 2 is a maximum value of relative number of delay samples in the signal amplification path,
M 1 is a maximum value of relative number of preceding samples in the power supply path,
M 2 is a maximum value of relative number of delay samples in the power supply path,
K m,l is a maximum order of characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l, and a coefficient relating to the relative delay (power supply path) m,
H k,l,m is a complex coefficient representing the characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l, a coefficient relating to the relative delay (power supply path) m, and a coefficient relating to the order k,
V[n−l−m] is a power supply voltage, and
u[n−l] is an input signal after subjected to distortion compensation.
6. The amplifier circuit according to claim 1 , wherein
the distortion compensation section also performs a process of compensating a third memory effect that occurs on a path from a signal output port of the distortion compensation section to the signal output port of the amplifier.
7. The amplifier circuit according to claim 1 , wherein
the model is an amplifier model based on the following equation:
y
[
n
]
=
∑
l
=
-
L
1
L
2
∑
m
=
-
M
1
M
2
∑
k
=
1
K
m
,
l
h
k
,
l
,
m
·
x
[
n
-
l
-
m
]
k
-
1
·
u
[
n
-
l
]
where
y[n] is an output of the amplifier at a time instance n, n being an integer,
k is an order,
l is a relative delay that occurs with respect to an input signal u[n] of the amplifier, in a path (hereinafter referred to as a “signal amplification path”) from a signal input port of the amplifier to a signal output port,
m is a relative delay that occurs with respect to the input signal u[n] of the amplifier, in a path (hereinafter referred to as a “power supply path”) from the power supply port of the amplifier to the signal output port,
L 1 is a maximum value of relative number of preceding samples in the signal amplification path,
L 2 is a maximum value of relative number of delay samples in the signal amplification path,
M 1 is a maximum value of relative number of preceding samples in the power supply path,
M 2 is a maximum value of relative number of delay samples in the power supply path,
K′ m,l is a maximum order of characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l, and a coefficient relating to the relative delay (power supply path) m,
h k,l,m is a complex coefficient representing the characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l, a coefficient relating to the relative delay (power supply path) m, and a coefficient relating to the order k,
V[n−l−m] is a power supply voltage, and
u[n−l] is an input signal after subjected to distortion compensation.
8. The amplifier circuit according to claim 1 , wherein
the distortion compensation section includes an estimation section that estimates an inverse model of the amplifier, and performs distortion compensation based on the inverse model estimated by the estimation section, and
the inverse model is an amplifier inverse model based on the following equation:
u
′
[
n
]
=
∑
l
=
-
L
1
L
2
∑
m
=
-
M
1
M
1
∑
k
=
1
Kc
m
,
l
hinv
k
,
l
,
m
y
[
n
-
l
-
m
]
k
-
1
·
y
[
n
-
l
]
where
u′[n] is an estimated value of an input signal u[n] of the amplifier, at a time instance n, n
k is an order,
l is a relative delay that occurs with respect to the input signal u[n] of the amplifier, in a path (hereinafter referred to as a “signal amplification path”) from a signal input port of the amplifier to a signal output port,
m is a relative delay that occurs with respect to the input signal u[n] of the amplifier, in a path (hereinafter referred to as a “power supply path”) from the power supply port of the amplifier to the signal output port,
L 1 is a maximum value of relative number of preceding samples in the signal amplification path,
L 2 is a maximum value of relative number of delay samples in the signal amplification path,
M 1 is a maximum value of relative number of preceding samples in the power supply path,
M 2 is a maximum value of relative number of delay samples in the power supply path,
Kc m,l is a maximum order of characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l, and a coefficient relating to the relative delay (power supply path) m,
hinv k,l,m is a complex coefficient representing inverse characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l, a coefficient relating to the relative delay (power supply path) m, and a coefficient relating to the order k, and
y[n−l−m], and y[n−l] are outputs of the amplifier.
9. Wireless communication equipment including the amplifier circuit according to claim 1 , for amplification of a transmission signal or amplification of a reception signal.
10. An amplifier circuit, comprising:
an amplifier that amplifies a signal; and
a distortion compensation section that includes an estimation section that estimates a model of the amplifier, and that performs compensation for distortion characteristics of the amplifier based on the model estimated by the estimation section, wherein
the model represents a memory effect that occurs on a path from an input port other than a signal input port of the amplifier, to a signal output port such that distortion compensation section performs a process of compensating the memory effect that occurs on the path from the input port other than the signal input port of the amplifier, to the signal output port, and
the process is performed on the signal to be inputted to the signal input port of the amplifier.
11. Wireless communication equipment including the amplifier circuit according to claim 10 , for amplification of a transmission signal or amplification of a reception signal.
12. An amplifier circuit, comprising:
an amplifier that amplifies a signal;
a variable power supply that varies a power supply voltage or a power supply current to be supplied to a power supply port of the amplifier, in accordance with change in an envelope of the signal; and
a distortion compensation section that includes an estimation section that estimates a model of the amplifier, and performs a process of distortion compensation based on the model estimated by the estimation section, wherein
in the model, the amplifier has nonlinear characteristic which is defined based on an input signal inputted to a signal input port of the amplifier, and the power supply voltage or the power supply current supplied from the variable power supply, the model represents at least a memory effect that occurs on a path from the power supply port to a signal output port of the amplifier, and
the process is performed on the signal to be inputted to a signal input port of the amplifier.
13. The amplifier circuit according to claim 12 , wherein
the model is an amplifier model based on the following equation:
Y
l
″
,
m
″
″
[
n
″
-
M
1
]
=
∑
k
=
1
K
l
″
-
L
1
,
m
″
-
M
1
H
k
,
l
″
-
L
1
,
m
″
-
M
1
·
V
[
n
″
-
l
″
-
m
″
]
k
-
1
·
u
[
n
″
-
l
″
-
M
1
]
where
Y″ l″,m″ [n″−M 1 ] is an output of the amplifier in the model at a time instance n, n being an integer,
k is an order,
l″ is a relative delay that occurs with respect to an input signal u[n″] of the amplifier, in a path (hereinafter referred to as a “signal amplification path”) from the signal input port of the amplifier to a signal output port,
m″ is a relative delay that occurs with respect to the input signal u[n″] of the amplifier, in a path (hereinafter referred to as a “power supply path”) from the power supply port of the amplifier to the signal output port,
L 1 is a maximum value of relative number of preceding samples in the signal amplification path,
M 1 is a maximum value of relative number of preceding samples in the power supply path,
K l″−L1,m″−M1 is a maximum order of characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l″−L 1 , and a coefficient relating to the relative delay (power supply path) m″−M 1 ,
H k,l″−L1,m″−M1 is a complex coefficient representing the characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l″−L 1 , a coefficient relating to the relative delay (power supply path) m″−M 1 , and a coefficient relating to the order k,
V[n″−l″−m″] is a power supply voltage, and
u[n″−l″−M 1 ] is an input signal after subjected to distortion compensation.
14. An amplifier circuit according to claim 12 , wherein
in the model, the amplifier is modeled as a combination of a plurality of nonlinear elements,
the plurality of nonlinear elements are each given the input signal inputted to the signal input port,
a combination of outputs from the plurality of nonlinear elements corresponds to the output of the amplifier,
the plurality of nonlinear elements each have nonlinear characteristic which is defined based on the input signal and the power supply voltage or the power supply current, and
the plurality of nonlinear elements are given the input signal at different times, respectively.
15. The amplifier circuit according to claim 14 , wherein
the model is an amplifier model based on the following equation:
Y
0
′
[
n
′
-
M
1
]
=
∑
l
′
=
-
L
1
L
2
Y
l
′
,
0
″
[
n
′
-
M
1
]
=
∑
l
′
=
-
L
1
L
2
∑
k
=
1
K
l
′
,
-
M
1
H
k
,
l
′
,
-
M
1
·
V
[
n
′
-
l
′
]
k
-
1
·
u
[
n
′
-
l
′
-
M
1
]
where
Y′ 0 [n′−M 1 ] is an output of the amplifier model at a time instance n, n being an integer,
k is an order,
l′ is a relative delay that occurs with respect to an input signal u of the amplifier, in a path (hereinafter referred to as a “signal amplification path”) from the signal input port of the amplifier to the signal output port,
L 1 is a maximum value of relative number of preceding samples in the signal amplification path,
L 2 is a maximum value of relative number of delay samples in the signal amplification path,
M 1 is a maximum value of relative number of preceding samples, in a path (hereinafter referred to as “power supply path”) from the power supply port of the amplifier to the signal output port,
K l″−L1,−M1 is a maximum order of characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l″−L 1 , and a coefficient relating to the relative delay (power supply path) −M 1 ,
H k,l″−L1,−M1 is a complex coefficient representing the characteristic of the amplifier, wherein indices are a coefficient relating to the relative delay (signal amplification path) l″−L 1 , a coefficient relating to the relative delay (power supply path) −M 1 , and a coefficient relating to the order k,
V[n″−l″] is a power supply voltage, and
u [n″−l″−M 1 ] is an input signal after subjected to distortion compensation.
16. Wireless communication equipment including the amplifier circuit according to claim 12 , for amplification of a transmission signal or amplification of a reception signal.
17. An amplifier circuit for amplifying a signal inputted thereto, comprising:
an amplifier; and
a distortion compensation section that includes an estimation section that estimates a model of the amplifier, and that performs distortion compensation of the amplifier based on the model estimated by the estimation section, wherein
the model represents memory effects that occur on a plurality of paths of the amplifier for amplifying the signal such that distortion compensation section performs a process of compensation of the memory effects in the plurality of paths for amplifying the signal, and
the process is performed on the signal to be inputted to a signal input port of the amplifier.
18. The amplifier circuit according to claim 17 , wherein
the plurality of paths include a first path which is a signal amplification path of the amplifier, and a second path which is a path for a signal that varies in accordance with change in an envelope of the inputted signal.
19. Wireless communication equipment including the amplifier circuit according to claim 17 , for amplification of a transmission signal or amplification of a reception signal.