Packet processing VLIW action unit with or-multi-ported instruction memory

1. An apparatus for packet processing in a switching network comprising:

a memory, the memory comprising:

a plurality of words wherein each word in the plurality of words has a plurality of bits wherein each word in the plurality of words is addressed by separate and distinct read address;

a logic circuit wherein all bits in the plurality of bits in each word in the plurality of words addressed by a separate and distinct read address are logically ORed together; wherein a result of ORing all bits in the plurality of bits in each word in the plurality of words addressed by a separate and distinct read address is output by the logic circuit;

wherein each of the read addresses further comprises:

an address ingress/egress bit wherein when the address ingress/egress bit is true the read address is associated with an ingress pipeline;

wherein when the address ingress/egress bit is false the read address is associated with an egress pipeline;

wherein an ingress wordline is enabled when the address ingress/egress bit is true; and

wherein an egress wordline is enabled when the address ingress/egress bit is false;

wherein each word in the plurality of words is an instruction word;

wherein each word in the plurality of words comprises a plurality of subwords;

wherein for each subword in the plurality of subwords there is a subword ingress/egress signal;

wherein the output of the logic circuit is enabled by the ingress wordline when the subword ingress/egress signal is high; and

wherein the output of the logic circuit is enabled by the egress wordline when the subword ingress/egress signal is low.

2. An apparatus for packet processing in a switching network comprising:

a memory, the memory comprising:

a plurality of words wherein each word in the plurality of words has a plurality of bits wherein each word in the plurality of words is addressed by separate and distinct read address;

a logic circuit wherein all bits in the plurality of bits in each word in the plurality of words addressed by a separate and distinct read address are logically ORed together; wherein a result of ORing all bits in the plurality of bits in each word in the plurality of words addressed by a separate and distinct read address is output by the logic circuit;

a plurality of data processors coupled to the memory;

receiving circuitry, the receiving circuitry being operable to receive packet headers vectors wherein each packet header vector comprises a plurality of header words;

wherein the plurality of data processors comprises at least one processor for each header word;

wherein the at least one data processor for each header word receives instructions from an instruction word; and

wherein each data processor in the plurality of data processors operates on a separate and distinct header word from the plurality of header words;

wherein each header word in the plurality of header words has an ingress/egress bit associated with each header word;

wherein when a subword ingress/egress signal is a logical high value, a header word is originates from an ingress pipleline; and

wherein when the subword ingress/egress signal is a logical low value, a header word is originates from an egress pipleline.