Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same

1. A microelectronic package comprising:

a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion;

a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer, wherein the stress relief barrier on at least the bottom portion of the glass interposer forms a single, continuous layer from about a first through via of the plurality of through vias to about a second through via of the plurality of through vias;

a metallization seed layer on at least a portion of the stress relief layer; and

a conductor on at least a portion of the metallization seed layer and through at least a portion of the plurality of the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

2. The microelectronic package of claim 1 , wherein the stress relief barrier comprises a polymer film.

3. The microelectronic package of claim 2 , wherein the polymer film comprises a thin dry film build up dielectric.

4. The microelectronic package of claim 2 , wherein the polymer film is deposited as a dry film, liquid coating, or vapor phase deposition thin film.

5. The microelectronic package of claim 1 , wherein the stress relief barrier has a coefficient of thermal expansion between the glass interposer and the conductor.

6. The microelectronic package of claim 1 , wherein the stress relief barrier is on at least a portion of the walls of the through vias in the glass interposer.

7. The microelectronic package of claim 1 , wherein the stress relief barrier and the metallization seed layer comprise the same material.

8. The microelectronic package of claim 7 , wherein the stress relief barrier and the metallization layer are selected from the group consisting of palladium, nickel, nickel allows, and copper alloys.

9. The microelectronic package of claim 1 , wherein at least a portion of the remaining portion of the through vias not filled with the stress relief barrier or the metallization seed layer are filled with a filler.

10. The microelectronic package of claim 9 , wherein the filler is selected from the group consisting of air, a polymer, a metal alloy, and any combination thereof.

11. The microelectronic package of claim 1 , wherein the conductor forms at least one interlock.

12. A microelectronic package, comprising:

a polymer on at least a portion of a top surface of a glass interposer and on at least a portion of a bottom surface of the glass interposer, wherein at least a portion of the polymer and the glass interposer are removed to form a through via;

a metallization seed layer on at least a portion of the polymer;

wherein at least a portion of the through via is filled with a metal conductor forming a metallization layer, wherein a portion of the metallization layer has been selectively removed to form a metalized through package via; and

wherein the polymer forms a first single, continuous layer on the at least a portion of the bottom surface of the glass interposer.

13. The microelectronic package of claim 12 , further comprising the metallization layer on at least a portion of a side wall of the through via.

14. The microelectronic package of claim 12 , wherein the polymer comprises resin-coated copper.

15. The microelectronic package of claim 12 , wherein the dielectric layer comprises a compliant build-up dielectric layer.

16. The microelectronic package of claim 1 , wherein the stress relief barrier on at least the bottom portion of the glass interposer forms a single, continuous layer from about a first through via of the plurality of vias to about a second through via of the plurality of vias.

17. The microelectronic package of claim 12 , wherein:

the polymer forms a first single, continuous layer on the at least a portion of the top surface of the glass interposer.