IP Library Granted Patent US 9,276,379
Granted Patent B2
US 9,276,379 · App. 14/495,904 · Granted Mar 1, 2016

Semiconductor light emitting device and method for manufacturing same

Inventors: Tomoya Satoh (Osaka, JP); Takeshi Yokoyama (Hyogo, JP); Shouichi Takasuka (Hyogo, JP); Isao Kidoguchi (Hyogo, JP)
Assignee: Panasonic Intellectual Property Management Co., Ltd.
H01S5/22B82Y20/00H01S5/3211H01S5/34313H01L21/28575H01L21/31679H01L23/53223H01S5/3215
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Quick Facts
Patent No.
US 9,276,379
App. No.
14/495,904
Granted
Mar 1, 2016
Kind
B2
Abstract

A semiconductor light emitting device includes a first conductive clad layer that is group III-V semiconductor mixed crystal, an active layer, and a second conductive clad layer. The second conductive clad layer has a laminated structure of at least three layers including a first layer, a second layer, and a third layer disposed in this order closer to the active layer. The second layer and the third layer are included in a striped ridge, and the second layer is positioned at a skirt of the ridge. The surface of the first layer is a flat part at both sides of the ridge. When Al compositions of the first layer, second layer, and third layer are X1, X2, and X3, respectively, the relation X2>X1, X3 is satisfied. When film thicknesses of the first layer, second layer, and third layer are D1, D2, and D3, the relation D2<D3 is satisfied.

Claims (83)

1. A III-V semiconductor light emitting device comprising a first conductive clad layer, an active layer, and a second conductive clad layer laminated on a substrate in this order closer to the substrate, wherein

the second conductive clad layer is an AlGaInP-based semiconductor mixed crystal and has a laminated structure of at least three layers, including a first layer, a second layer, and a third layer disposed in this order closer to the active layer,

the second layer and the third layer are included in a striped ridge, and the second layer is positioned at a skirt of the ridge,

the first layer has a flat surface under both sides of the striped ridge and parallel to the active layer,

Al compositions X1, X2, and X3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

X2>X1 and X2>X3, and

film thicknesses D1, D2, and D3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

D2<D3.

2. The III-V semiconductor light emitting device of claim 1 ,

wherein

a side wall of the third layer is substantially perpendicular to a plane of the substrate.

3. The III-V semiconductor light emitting device of claim 1 ,

wherein

a slope of a side wall of the second layer is gentler at a lower part of the second layer than at an upper part of the second layer.

4. The III-V semiconductor light emitting device of claim 3 ,

wherein

the slope of the side wall of the second layer has a shape substantially perpendicular to a surface of the substrate at its upper part, and a shape flaring downward at its lower part.

5. The III-V semiconductor light emitting device of claim 1 ,

wherein

the third layer is a laminated film of a plurality of laminated layers having smaller Al composition than the second layer, and the D3 is a total film thickness of the plurality of laminated layers.

6. The III-V semiconductor light emitting device of claim 1 ,

wherein

the D2 is not less than 200 nm and not greater than 500 nm.

7. The III-V semiconductor light emitting device of claim 1 ,

wherein

the first layer, the second layer, and the third layer are formed of AlGaInP.

8. The III-V semiconductor light emitting device of claim 1 ,

wherein

the third layer to an upper part of the second layer are processed into a stripe shape by non-selective etching, and a lower part of the second layer is processed into a stripe shape by selective etching.

9. The III-V semiconductor light emitting device of claim 8 ,

wherein

the non-selective etching is dry etching, and the selective etching is wet etching.

10. A method for manufacturing a III-V semiconductor light emitting device, the method comprising:

forming on a substrate a first conductive clad layer, an active layer, and a second conductive clad layer, the second conductive clad layer is an AlGaInP-based semiconductor mixed crystal and has a laminated structure of at least three layers including a first layer, a second layer, and a third layer disposed in an order closer to the active layer;

processing the third layer to an upper part of the second layer into a stripe shape by non-selective etching; and

processing a lower part of the second layer into a stripe shape by selective etching,

wherein

Al compositions X1, X2, and X3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

X2>X1 and X2>X3, and

film thicknesses D1, D2, and D3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

D2<D3.

11. The method for manufacturing the III-V semiconductor light emitting device of claim 10 ,

wherein

a slope of a side wall of the third layer formed by the step of processing the stripe shape is substantially perpendicular to a plane of the substrate.

12. The method for manufacturing the III-V semiconductor light emitting device of claim 10 ,

wherein

a slope of a side wall of the second layer formed by the step of processing into the stripe shape is gentler at the lower part than at the upper part.

13. The III-V semiconductor light emitting device of claim 12 ,

wherein

the slope of the side wall of the second layer has a shape substantially perpendicular to a surface of the substrate at its upper part, and a tapered shape spreading downward at its lower part.

14. The method for manufacturing the III-V semiconductor light emitting device of claim 10 ,

wherein

the D2 is not less than 200 nm and not greater than 500 nm.

15. The method for manufacturing the III-V light emitting device of claim 10 ,

wherein

the first layer and the second layer are both formed of AlGaInP, the X1 is not greater than 0.35, and the X2 is not less than 0.55.

16. The method for manufacturing the III-V semiconductor light emitting device of claim 10 ,

wherein

the non-selective etching is dry etching, and the selective etching is wet etching.

17. The III-V semiconductor light emitting device of claim 1 , wherein the X1 is not greater than or equal to 0.35, and the X2 is not less than 0.55.

18. The III-V semiconductor light emitting device of claim 1 , wherein a sidewall of the striped ridge is covered by a current blocking layer, and the current blocking layer is in direct contact with the flat surface of the first layer.

19. The III-V semiconductor light emitting device of claim 1 , wherein the first conductive clad layer is an AlGaInP-based semiconductor mixed-crystal.

20. The III-V semiconductor light emitting device of claim 1 , wherein all the Al compositions X1, X2, and X3 are greater than 0.

21. The method for manufacturing the III-V light emitting device of claim 10 , wherein all the Al compositions X1, X2, and X3 are greater than 0.

22. A III-V semiconductor light emitting device comprising a first conductive clad layer, an active layer, and a second conductive clad layer laminated on a substrate in this order closer to the substrate, wherein

the second conductive clad layer has a laminated structure of at least three layers, including a first layer, a second layer, and a third layer disposed in this order closer to the active layer,

the second layer and the third layer are included in a striped ridge, and the second layer is positioned at a skirt of the ridge,

the first layer has a flat surface under both sides of the striped ridge and parallel to the active layer,

Al compositions X1, X2, and X3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

X2>X1 and X2>X3,

all the Al compositions X1, X2, and X3 are greater than 0, and

film thicknesses D1, D2, and D3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

D2<D3.

23. A method for manufacturing a III-V semiconductor light emitting device, the method comprising:

forming on a substrate a first conductive clad layer, an active layer, and a second conductive clad layer, the second conductive clad layer has a laminated structure of at least three layers including a first layer, a second layer, and a third layer disposed in an order closer to the active layer;

processing the third layer to an upper part of the second layer into a stripe shape by non-selective etching; and

processing a lower part of the second layer into a stripe shape by selective etching,

wherein

Al compositions X1, X2, and X3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

X2>X1 and X2>X3,

all the Al compositions X1, X2, and X3 are greater than 0, and

film thicknesses D1, D2, and D3 of the first layer, the second layer, and the third layer, respectively, satisfy a relation:

D2<D3.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2014
From: SATOH, TOMOYA; YOKOYAMA, TAKESHI; TAKASUKA, SHOUICHI; KIDOGUCHI, ISAO
To: PANASONIC CORPORATION
Reel/Frame 033907/0027 →
Priority Claims (1)
JP 2012-240181 · Oct 31, 2012 · national
Continuity (2)
Continuation PCTJP2013004258 · Jul 10, 2013
Related Publication 20150043604A1 · Feb 12, 2015