IP Library › Granted Patent US 9,277,648
Granted Patent B2
US 9,277,648 · App. 14/570,290 · Granted Mar 1, 2016

Printed wiring board and information processing apparatus

Inventors: Shotaro Hamao (Kawasaki, JP); Yoshiaki Tamura (Kawasaki, JP); Toshiki Kurosawa (Kawasaki, JP)
Assignee: FUJITSU LIMITED
H05K1/115H05K2201/0391
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Quick Facts
Patent No.
US 9,277,648
App. No.
14/570,290
Granted
Mar 1, 2016
Kind
B2
Abstract

A printed wiring board having a land for surface-mounting of an electronic component, includes the land having a pair of land pieces arranged in an opposing manner, and each of the land pieces including a plurality of land portions having widths different from each other, and a coupling portion partially coupling a boundary portion between a pair of adjacent ones of the land portions.

Claims (14)

1. A printed wiring board having a land for surface-mounting of an electronic component, comprising:

the land having a pair of land pieces arranged in an opposing manner, and

each of the land pieces including

a plurality of land portions having widths different from each other, and

a coupling portion partially coupling a boundary portion between a pair of adjacent ones of the land portions, wherein

in the boundary portion between the pair of land portions, a plurality of resist portions for suppressing a flow of solder between the pair of land portions are arranged along a width direction of the land pieces, and the coupling portion is disposed between adjacent ones of the resist portions.

2. The printed wiring board according to claim 1 , wherein in the boundary portion between the pair of land portions, a plurality of the coupling portions are arranged along the width direction.

3. The printed wiring board according to claim 1 , wherein widths of the plurality of land portions in the land pieces respectively correspond to widths of a plurality of electronic components having different sizes.

4. An information processing apparatus including a printed wiring board having a land for surface-mounting of an electronic component, wherein

the land has a pair of land pieces, and

each of the land pieces includes

a plurality of land portions having widths different from each other, and

a coupling portion partially coupling a boundary portion between a pair of adjacent ones of the land portions, and wherein

in the boundary portion between the pair of land portions, a plurality of resist portions for suppressing a flow of solder between the pair of land portions are arranged along a width direction of the land pieces, and the coupling portion is disposed between adjacent ones of the resist portions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2019
From: FUJITSU LIMITED
To: FUJITSU CLIENT COMPUTING LIMITED
Reel/Frame 048751/0051 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2014
From: HAMAO, SHOTARO; TAMURA, YOSHIAKI; KUROSAWA, TOSHIKI
To: FUJITSU LIMITED
Reel/Frame 034508/0875 →
Priority Claims (1)
JP 2014-006969 · Jan 17, 2014 · national
Continuity (1)
Related Publication 20150208503A1 · Jul 23, 2015