Mechanism for forming gate
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.
1. A semiconductor device, comprising:
a semiconductor substrate;
an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate;
a gate over the semiconductor substrate, wherein the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are located over the isolation structure, each of the end portions has a first gate length longer than a second gate length of the intermediate portion, and each of the end portions has a first edge facing the active region and aligned with a second edge of the isolation structure; and
a spacer layer surrounding and covering an entire lateral outer sidewall of the intermediate portion of the gate and an entire lateral outer side wall of the two end portions of the gate, wherein the spacer layer that covers the entire lateral outer side wall of the two end portions of the gate has a first portion located directly above the active region and a second portion located directly above the isolation structure.
2. The semiconductor device as claimed in claim 1 , wherein a ratio of the second gate length of the intermediate portion to the first gate length of the end portion ranges from about 10% to about 95%.
3. The semiconductor device as claimed in claim 1 , wherein a ratio of the second gate length of the intermediate portion to the first gate length of the end portion ranges from about 50% to about 80%.
4. The semiconductor device as claimed in claim 1 , wherein the whole intermediate portion is located over the active region.
5. The semiconductor device as claimed in claim 1 , wherein the end portions have the same width.
6. The semiconductor device as claimed in claim 1 , wherein the end portions have different widths.
7. The semiconductor device as claimed in claim 1 , wherein the second gate length of the intermediate portion is shorter than about 100 nm.
8. The semiconductor device as claimed in claim 1 , wherein the gate extends across the active region.
9. A semiconductor device, comprising:
a semiconductor substrate;
an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate;
a gate over the semiconductor substrate, wherein the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are located over the isolation structure, each of the end portions has a first gate length longer than a second gate length of the intermediate portion, the active region is between the end portions, and each of the end portions has a first edge facing the active region and aligned with a second edge of the isolation structure; and
a spacer layer surrounding and covering an entire lateral outer sidewall of the intermediate portion of the gate and an entire lateral outer side wall of the two end portions of the gate, wherein the spacer layer that covers the entire lateral outer side wall of the two end portions of the gate has a first portion located directly above the active region and a second portion located directly above the isolation structure.
10. The semiconductor device as claimed in claim 9 , wherein the end portions have the same width.
11. The semiconductor device as claimed in claim 9 , wherein a ratio of the second gate length of the intermediate portion to the first gate length of the end portion ranges from about 50% to about 80%.
12. The semiconductor device as claimed in claim 9 , wherein the gate extends across the active region.
13. The semiconductor device as claimed in claim 9 , wherein the whole intermediate portion is located over the active region.