Package process of backside illumination image sensor
View Patent ↗In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.
1. A method of processing a wafer, the method comprising:
forming a plurality of through holes within a first carrier, wherein the first carrier includes a front surface and a rear surface opposite the front surface, and wherein the plurality of through holes penetrate the front surface and the rear surface, including:
forming an oxide layer on the front surface of the first carrier;
removing a portion of the oxide layer to expose a portion of the front surface of the first carrier; and
forming one of the plurality of through holes in the first carrier within an area of the front surface exposed by said removing a portion of the oxide layer;
adhering the front surface of the first carrier to a first surface of a wafer so that the formed plurality of through holes face a plurality of respective pads formed on the wafer and expose the plurality of respective pads therefrom;
forming a spacing layer on a second surface of the wafer, wherein the spacing layer includes an open region to expose the second surface therefrom;
disposing a plurality of optical components in the open region, wherein the spacing layer comprises a patterned adhesive layer that extends farther from the second surface of the wafer than the plurality of optical components;
adhering a second carrier to the spacing layer; and
thinning the wafer prior to said forming a spacing layer, wherein said thinning the wafer includes:
grinding the second surface of the wafer to form a grinding surface; and
etching the grinding surface.
2. The method of claim 1 , wherein the first carrier comprises a silicon substrate, and wherein the oxide layer comprises a silicon oxide layer.
3. The method of claim 1 , further comprising:
forming an insulating layer on the first carrier covering the rear surface and sidewalls of the plurality of through holes; and
forming an electrically-conductive layer on the insulating layer within the plurality of though holes so that the electrically-conductive layer is electrically connected to the plurality of respective pads.
4. The method of claim 3 , wherein the insulating layer comprises a silicon oxide layer.
5. The method of claim 3 , wherein said forming an insulating layer comprises:
forming an insulating material on the rear surface of the first carrier to cover the rear surface, the plurality of respective pads, and the sidewalls of the plurality of through holes; and
etching the insulating material to remove portions of the insulating material on the plurality of respective pads.
6. The method of claim 1 , wherein said forming a plurality of through holes within a first carrier is performed prior to said adhering the front surface of the first carrier to a first surface of a wafer.
7. The method of claim 1 , wherein the plurality of through holes are devoid of electrically-conductive material during said adhering the front surface of the first carrier to a first surface of a wafer.
8. The method of claim 1 , wherein the plurality of through holes are unfilled during said adhering the front surface of the first carrier to a first surface of a wafer.
9. The method of claim 1 , further comprising, after said adhering the front surface of the first carrier to a first surface of a wafer, forming an electrically-conductive material within at least one of the plurality of through holes, wherein the electrically-conductive material is in physical contact with at least one of the plurality of respective pads.
10. The method of claim 1 , wherein the second surface of the wafer is opposite the first surface of the wafer.
11. The method of claim 3 , wherein said forming an insulating layer on the first carrier covering the rear surface and sidewalls of the plurality of through holes comprises completely covering the rear surface and the sidewalls of the plurality of through holes with the insulating layer.
12. The method of claim 1 , wherein the plurality of optical components comprises a plurality of sensing components.
13. The method of claim 12 , wherein the plurality of sensing components comprises a photodiode, a color filter, and a micro lens.
14. The method of claim 13 , wherein said disposing the plurality of optical components in the open region comprises:
disposing the photodiode on the second surface of the wafer;
forming the color filter over the photodiode; and
disposing the micro lens over the color filter.