Scheduling in a multicore architecture
View Patent ↗The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.
1. A method of scheduling threads, the method comprising:
analyzing, by a parent scheduler, an application to identify an application thread for execution, the parent scheduler associated with a plurality of associated child schedulers, the parent scheduler configured to store a pointer to a most eligible child scheduler;
providing, by the parent scheduler, the application thread to the most eligible child scheduler based on the stored pointer, the most eligible child scheduler determined based on priority metrics received from each child scheduler; and
scheduling, by the most eligible child scheduler, the application thread for execution by a processor core of a multicore processor associated with the most eligible child scheduler.
2. The method of claim 1 , wherein analyzing the application comprises analyzing the application during the execution of the application.
3. The method of claim 1 , wherein analyzing the application comprises analyzing the application in response to an event comprising of one or more of: a push event, a pop event, an update event, an interrupt, an arrival of a new task, a synchronization event, a change to a priority assigned to a task, a consumption of a task, a modification to a metric associated with a task, a modification to scheduling a processor, and a modification to an organization of the parent scheduler and/or one or more child schedulers.
4. The method of claim 1 , wherein analyzing the application comprises identifying the application thread using one or more thread queues.
5. The method of claim 1 , wherein the processor core comprises reconfigurable logic, and wherein the application thread is configured to be executed by a particular configuration of the reconfigurable logic.
6. The method of claim 5 , wherein the reconfigurable logic comprises a field programmable gate array (FPGA).
7. A non-transitory computer readable storage medium storing computer-executable program code that, when executed by a processor, causes the processor to perform steps comprising:
analyzing, by a parent scheduler, an application to identify an application thread for execution, the parent scheduler associated with a plurality of associated child schedulers, the parent scheduler configured to store a pointer to a most eligible child scheduler;
providing, by the parent scheduler, the application thread to the most eligible child scheduler based on the stored pointer, the most eligible child scheduler determined based on priority metrics received from each child scheduler; and
scheduling, by the most eligible child scheduler, the application thread for execution by a processor core of a multicore processor associated with the most eligible child scheduler.
8. The computer readable storage medium of claim 7 , wherein analyzing the application comprises analyzing the application during the execution of the application.
9. The computer readable storage medium of claim 7 , wherein analyzing the application comprises analyzing the application in response to an event comprising of one or more of: a push event, a pop event, an update event, an interrupt, an arrival of a new task, a synchronization event, a change to a priority assigned to a task, a consumption of a task, a modification to a metric associated with a task, a modification to scheduling a processor, and a modification to an organization of the parent scheduler and/or one or more child schedulers.
10. The computer readable storage medium of claim 7 , wherein analyzing the application comprises identifying the application thread using one or more thread queues.
11. The computer readable storage medium of claim 7 , wherein the processor core comprises reconfigurable logic, and wherein the application thread is configured to be executed by a particular configuration of the reconfigurable logic.
12. The computer readable storage medium of claim 11 , wherein the reconfigurable logic comprises a field programmable gate array (FPGA).
13. A system for scheduling threads, the circuit comprising:
a parent scheduler configured to:
analyze an application to identify an application thread for execution;
store a pointer to a most eligible child scheduler; and
provide the application thread to the most eligible child scheduler based on the stored pointer;
a plurality of child schedulers associated with the parent scheduler, the plurality of child schedulers comprising the most eligible child scheduler, the most eligible child scheduler configured to schedule the application thread for execution, each child scheduler configured to provide priority metrics to the parent scheduler, the most eligible child scheduler determined based on the provided priority metrics; and
a processor core of a multicore processor associated with the most eligible child scheduler and configured to execute the application thread in response to the application thread being scheduled for execution by the most eligible child scheduler.
14. The system of claim 13 , wherein analyzing the application comprises analyzing the application during the execution of the application.
15. The system of claim 13 , wherein analyzing the application comprises analyzing the application in response to an event comprising of one or more of: a push event, a pop event, an update event, an interrupt, an arrival of a new task, a synchronization event, a change to a priority assigned to a task, a consumption of a task, a modification to a metric associated with a task, a modification to scheduling a processor, and a modification to an organization of the parent scheduler and/or one or more child schedulers.
16. The system of claim 13 , wherein analyzing the application comprises identifying the application thread using one or more thread queues.
17. The system of claim 13 , wherein the processor core comprises reconfigurable logic, and wherein the application thread is configured to be executed by a particular configuration of the reconfigurable logic.
18. The system of claim 17 , wherein the reconfigurable logic comprises a field programmable gate array (FPGA).