IP Library › Assignment 075801/0204
Patent Assignment
Reel/Frame 075801/0204

Assignment of Assignor's Interest

Recorded: 2026-06-23 Pages: 21
Assignor
SYNOPSYS, INC.
Executed: 2026-06-01
Assignee
MIPS HOLDING, INC.
2870 ZANKER ROAD, #210, SAN JOSE, CALIFORNIA, 95134
Covered Properties (50)
Automatic Generation of Transaction Level Bus Simulation Instructions from Bus Protocol
Patent: 8,090,564 →
Application: 10/700,601 →
Method of Protocol Conversion Between Synchronous Protocols That Are Suitable for Synthesis
Patent: 7,512,732 →
Application: 10/700,600 →
Processor/Memory Co-Exploration at Multiple Abstraction Levels
Patent: 7,788,078 →
Application: 11/069,496 →
Generation of instruction set from architecture description
Patent: 8,595,688 →
Application: 10/936,230 →
Generation of compiler description from architecture description
Patent: 8,677,312 →
Application: 10/815,228 →
Scheduling of Instructions
Patent: 8,689,202 →
Application: 11/096,184 →
Compiler Retargeting Based on Instruction Semantic Models
Patent: 9,280,326 →
Application: 11/140,353 →
Transaction Level Model Synthesis
Patent: 8,413,106 →
Application: 10/976,402 →
Efficient Clock Models and Their Use in Simulation
Patent: 8,036,873 →
Application: 11/069,616 →
Publication: US US20060195310A1
Method and System for Automatic Generation of Instruction-Set Documentation from an Abstract Processor Model Described Using a Hierarchical Architectural Description Language
Patent: 8,006,225 →
Application: 11/145,240 →
Interface Converter for Unified View of Multiple Computer System Simulations
Patent: 7,716,031 →
Application: 11/066,841 →
Publication: US US20060195821A1
Scalable Language Infrastructure for Electronic System Level Tools
Patent: 8,856,731 →
Application: 13/356,472 →
Publication: US US20130024839A1
Method and System for Dynamically Adjusting Speed Versus Accuracy of Computer Platform Simulation
Patent: 7,742,905 →
Application: 11/066,945 →
Publication: US US20060195825A1
Method and Device for Simulator Generation Based on Semantic to Behavioral Translation
Patent: 7,313,773 →
Application: 11/139,373 →
User interface for facilitation of high level generation of processor extensions
Patent: 9,064,076 →
Application: 11/388,484 →
Dynamic host code generation from architecture description for fast simulation
Patent: 9,830,174 →
Application: 11/584,402 →
Publication: US US20070150873A1
Simulation with Dynamic Run-Time Accuracy Adjustment
Patent: 8,543,367 →
Application: 11/707,412 →
Simulation with Dynamic Run-Time Accuracy Adjustment
Patent: 9,471,727 →
Application: 13/974,735 →
Publication: US US20130346046A1
Caching Information to Map Simulation Addresses to Host Addresses in Computer System Simulations
Patent: 8,650,012 →
Application: 13/019,197 →
Caching Information to Map Simulation Addresses to Host Addresses in Computer System Simulations
Patent: 7,881,921 →
Application: 11/824,880 →
Method and system for instruction set simulation with concurrent attachment of multiple debuggers
Patent: 8,914,274 →
Application: 11/637,418 →
System and method for stopping integrated circuit simulation
Patent: 9,317,636 →
Application: 11/637,374 →
Resource Management in a Multicore Architecture
Patent: 8,533,716 →
Application: 10/816,328 →
Publication: US US20050223382A1
Resource Management in a Multicore Architecture
Application: 13/965,113 →
Publication: US US20140026141A1
Debug in a Multicore Architecture
Patent: 9,038,070 →
Application: 10/941,457 →
Publication: US US20060069953A1
Scheduling in a multicore processor
Patent: 8,732,439 →
Application: 11/540,146 →
Publication: US US20070220517A1
Scheduling in a multicore architecture
Patent: 8,751,773 →
Application: 13/965,124 →
Publication: US US20140068619A1
Scheduling in a multicore architecture
Patent: 9,286,262 →
Application: 14/245,981 →
Publication: US US20140282593A1
Scheduling in a Multicore Architecture
Patent: 9,164,953 →
Application: 14/267,830 →
Publication: US US20140317378A1
Scheduling in a Multicore Architecture
Patent: 9,442,886 →
Application: 14/848,334 →
Publication: US US20150378776A1
Managing Power Consumption in a Multicore Processor
Patent: 8,533,503 →
Application: 11/541,315 →
Publication: US US20070220294A1
Techniques for Creating and Using a Hierarchical Data Structure
Patent: 9,697,211 →
Application: 11/607,243 →
Techniques for Coordinating and Controlling Debuggers in a Simulation Environment
Patent: 8,423,959 →
Application: 11/637,376 →
Coordinating and Controlling Debuggers in a Simulation Environment
Patent: 8,972,944 →
Application: 13/802,712 →
Publication: US US20130212566A1
System and Method of Debugging Multi-Threaded Processes
Patent: 8,683,444 →
Application: 12/001,238 →
System and Method of Debugging Multi-Threaded Processes
Patent: 9,459,992 →
Application: 14/165,541 →
Publication: US US20140196014A1
System and Method of Debugging Multi-Threaded Processes
Application: 15/251,925 →
Publication: US US20170004068A1
Run-Time Switching for Simulation with Dynamic Run-Time Accuracy Adjustment
Patent: 7,899,661 →
Application: 11/707,413 →
Publication: US US20070192079A1
Run-Time Switching for Simulation with Dynamic Run-Time Accuracy Adjustment
Patent: 8,521,499 →
Application: 13/038,152 →
Simulation Control Techniques
Patent: 8,397,220 →
Application: 12/030,192 →
Simulation Control Techniques
Patent: 8,856,756 →
Application: 13/791,905 →
Publication: US US20130191346A1
Memory Arbiter with Latency Guarantees for Multiple Ports
Patent: 8,745,335 →
Application: 13/171,484 →
Publication: US US20130007386A1
Visual Quality Measure for Real-Time Video Processing
Patent: 9,338,463 →
Application: 13/451,413 →
Publication: US US20130089150A1
Visual Quality Measure for Real-Time Video Processing
Application: 15/093,741 →
Publication: US US20160227220A1
Rate Distortion Optimization in Image and Video Encoding
Patent: 9,781,449 →
Application: 13/448,224 →
Publication: US US20130089137A1
Inter-Processor Communication Method
Patent: 8,006,069 →
Application: 11/973,173 →
Publication: US US20080086626A1
Microprocessor architecture having extendible logic
Patent: 8,719,837 →
Application: 11/132,424 →
Publication: US US20050289321A1
Systems and Methods for Performing Deblocking in Microprocessor-Based Video Codec Applications
Patent: 7,747,088 →
Application: 11/528,327 →
Publication: US US20070071106A1
Microprocessor System and Method for Instruction-Initiated Recording and Execution of Instruction Sequences in a Dynamically Decoupleable Extended Instruction Pipeline
Patent: 7,971,042 →
Application: 11/528,338 →
Publication: US US20070074012A1
Systems and Methods for Accelerating Sub-Pixel Interpolation in Video Processing Applications
Patent: 8,212,823 →
Application: 11/528,325 →
Publication: US US20070070080A1
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 22, 2004
From: MICHIELS, TOM; VAN ROMPAEY, KARL
To: COWARE, INC.
Reel/Frame 015119/0196 →
Assignment of Assignor's Interest Mar 31, 2004
From: BRAUN, GUNNAR; HOFFMANN, ANDREAS; GREIVE, VOLKER
To: COWARE, INC.
Reel/Frame 015180/0368 →
Assignment of Assignor's Interest Apr 19, 2004
From: GOOSSENS, SERGE
To: COWARE, INC.
Reel/Frame 015226/0466 →
Assignment of Assignor's Interest Oct 28, 2004
From: GOOSSENS, SERGE
To: COWARE, INC.
Reel/Frame 015943/0028 →
Security Agreement Jan 3, 2005
From: COWARE, INC.
To: VENTURE LENDING & LEASING IV, INC.
Reel/Frame 016116/0011 →
Assignment of Assignor's Interest Mar 30, 2005
From: BRAUN, GUNNAR; HOFFMANN, ANDREAS; GREIVE, VOLKER; HOHENAUER, MANUEL
To: COWARE, INC.
Reel/Frame 016442/0958 →
Assignment of Assignor's Interest Apr 1, 2005
From: GRIEVE,VOLKER; NOHL, ACHIM
To: COWARE, INC.
Reel/Frame 016415/0440 →
Assignment of Assignor's Interest Jun 3, 2005
From: VERMEERSCH, DIRK; ROMPAY, KARL VAN
To: COWARE, INC.
Reel/Frame 016646/0127 →
Assignment of Assignor's Interest Jun 3, 2005
From: VANSPAUWEN, NIELS; MICHIELS, TOM; VAN ROMPAEY, KARL
To: COWARE, INC.
Reel/Frame 016646/0076 →
Assignment of Assignor's Interest Jun 6, 2005
From: VANSPAUWEN, NIELS; MICHIELS, TOM; VAN ROMPAEY, KARL
To: COWARE, INC.
Reel/Frame 016654/0197 →
Assignment of Assignor's Interest Sep 1, 2005
From: BRAUN, GUNNAR; GREIVE, VOLKER; HOFFMANN, ANDREAS
To: COWARE, INC.
Reel/Frame 016942/0497 →
Assignment of Assignor's Interest Sep 23, 2005
From: BRAUN, GUNNAR; NOHL, ACHIM; CENG, JIANGJIANG; HOFFMANN, ANDREAS
To: COWARE, INC.
Reel/Frame 017540/0711 →
Re-Record to Correct Inventor Name Previously Recorded at Reel/Frame 016415/0440 Nov 1, 2005
From: GREIVE, VOLKER; NOHL, ACHIM
To: COWARE, INC.
Reel/Frame 016904/0418 →
Assignment of Assignor's Interest Dec 9, 2005
From: BRAUN, GUNNAR; HOFFMANN, ANDREAS; GREIVE, VOLKER; LEUPERS, RAINER
To: COWARE, INC.
Reel/Frame 017327/0021 →
Assignment of Assignor's Interest Jul 13, 2006
From: BRAUN, GUNNAR; FIEDLER, FRANK; HOFFMANN, ANDREAS; INTRATER, GIDEON
To: MIPS TECHNOLOGIES, INC.; COWARE, INC.
Reel/Frame 018091/0548 →
Corrective Assignment to Correct Name of Inventor Karl Aug 4, 2006
From: VERMEERSCH, DIRK; VAN ROMPAY, KARL
To: COWARE, INC.
Reel/Frame 018147/0200 →
Assignment of Assignor's Interest Sep 11, 2006
From: BRAUN, GUNNAR; FIEDLER, FRANK; HOFFMANN, ANDREAS; INTRATER, GIDEON
To: MIPS TECHNOLOGIES, INC.; COWARE, INC.
Reel/Frame 018280/0806 →
Assignment of Assignor's Interest Oct 19, 2006
From: VAN DAMME, JACQUES; NOHL, ACHIM; LUTHJE, OLAF
To: COWARE, INC.
Reel/Frame 018448/0380 →
Assignment of Assignor's Interest Dec 11, 2006
From: PETRAS, DIETMAR; VANSPAUWEN, NIELS
To: COWARE, INC.
Reel/Frame 018704/0389 →
Assignment of Assignor's Interest Dec 11, 2006
From: PETRAS, DIETMAR
To: COWARE, INC.
Reel/Frame 018708/0209 →
Assignment of Assignor's Interest Feb 16, 2007
From: VAN ROMPAEY, KARL; WIEFERINK, ANDREAS
To: COWARE, INC.
Reel/Frame 019003/0172 →
Assignment of Assignor's Interest Jul 2, 2007
From: DOBBELAERE, JEROEN
To: COWARE, INC.
Reel/Frame 019579/0025 →
Security Agreement Aug 24, 2007
From: MIPS TECHNOLOGIES, INC.
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 019744/0001 →
Security Agreement Jan 2, 2008
From: COWARE, INC.
To: SILICON VALLEY BANK
Reel/Frame 020308/0157 →
Security Agreement Jan 2, 2008
From: COWARE, INC.
To: GOLD HILL VENTURE LENDING 03, L.P.; SILICON VALLEY BANK
Reel/Frame 020308/0236 →