Systems and methods for 100 percent duty cycle in switching regulators

1. A buck switching regulator circuit comprising:

a first switching transistor having an input terminal to receive an input voltage and an output terminal coupled to an output node through an inductor;

a ramp generator to produce a ramp signal having a period; and

a comparator to receive the ramp signal and an error signal, and in accordance therewith, produce a modulation signal,

wherein, in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increases above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for a period of time greater than one or more full periods of the ramp signal, and wherein the first switching transistor remains turned on when the error signal is greater than a maximum value of the ramp signal, wherein a current through the inductor to the output node increases continuously across multiple periods of the ramp signal when the error signal is above the maximum value of the ramp signal.

2. The circuit of claim 1 wherein the error signal is generated by an error amplifier having a first input coupled to receive a feedback voltage from the output node and a second input coupled to a reference voltage.

3. The circuit of claim 1 , the ramp generator comprising:

a current source;

a capacitor having a terminal coupled to the current source; and

a switch,

wherein the magnitude of the current source is configured to set said maximum value of the ramp signal to be less than a maximum value of the error signal.

4. The circuit of claim 1 wherein the ramp generator receives a reset signal, wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when the reset signal is in a second state, and wherein a time period of the second state of the reset signal is configured to set said maximum value of the ramp signal to be less than a maximum value of the error signal.

5. The circuit of claim 4 further comprising a divider circuit to receive a clock signal and produce the reset signal, the clock signal setting the period of the ramp signal.

6. The circuit of claim 1 , the ramp generator further comprising a current feedback circuit to sense a current in the buck switching regulator and produce an offset in the ramp signal, wherein said maximum value of the ramp signal is less than a maximum value of the error signal.

7. The circuit of claim 6 , the ramp generator comprising:

a current source;

a capacitor having a terminal coupled to the current source;

a switch; and

an OR gate having a first input coupled to receive a reset signal and a second input coupled to receive the modulation signal, wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when the reset signal is in a second state;

wherein the magnitude of the current source and the offset are configured to set said maximum value to be less than a maximum value of the error signal.

8. A method comprising:

receiving an input voltage on an input terminal of a first switching transistor of a buck switching regulator, the first switching transistor having an output terminal coupled to an output node through an inductor;

generating a ramp signal having a period; and

comparing the ramp signal and an error signal to produce a modulation signal,

wherein in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increases above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for a period of time greater than one or more full periods of the ramp signal, and wherein the first switching transistor remains turned on when the error signal is greater than a maximum value of the ramp signal, wherein a current through the inductor to the output node increases continuously across multiple periods of the ramp signal when the error signal is above the maximum value of the ramp signal.

9. The method of claim 8 wherein the error signal is generated based on a feedback voltage from the output node and a reference voltage.

10. The method of claim 8 , generating the ramp signal comprising:

generating a current into a capacitor; and

discharging the capacitor in response to a first signal,

wherein the magnitude of the current is configured to set said maximum value of the ramp signal to be less than a maximum value of the error signal.

11. The method of claim 8 , generating the ramp signal comprising:

receiving a reset signal, wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when the reset signal is in a second state, and wherein a time period of the second state of the reset signal is configured to set said maximum value of the ramp signal to be less than a maximum value of the error signal.

12. The method of claim 11 further comprising dividing a clock signal and producing the reset signal, the clock signal setting the period of the ramp signal.

13. The method of claim 8 further comprising:

sensing a current in the buck switching regulator; and

producing an offset in the ramp signal based on the sensed current, wherein said maximum value of the ramp signal is less than a maximum value of the error signal.

14. The method of claim 13 , generating the ramp signal comprising:

generating a current into a capacitor; and

discharging the capacitor in response to a logical OR of a reset signal and the modulation signal,

wherein the ramp signal has a constant value when the reset signal is in a first state, and wherein the ramp signal increases to said maximum value when both the reset signal and modulation signal are in a second state;

wherein the magnitude of the current source and the offset are configured to set said maximum value of the ramp signal to be less than a maximum value of the error signal.

15. A buck switching regulator circuit comprising:

a first switching transistor having an input terminal to receive an input voltage and an output terminal coupled to an output node through an inductor;

means for generating a ramp signal, the ramp signal having a period; and

means for comparing the ramp signal and an error signal to produce a modulation signal,

wherein in a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of the first switching transistor during each period of the ramp signal, and in a second mode of operation, the error signal increases above a maximum value of the ramp signal, and in accordance therewith, the first switching transistor is turned on for a period of time greater than one or more full periods of the ramp signal, and wherein the first switching transistor remains turned on when the error signal is greater than a maximum value of the ramp signal, wherein a current through the inductor to the output node increases continuously across multiple periods of the ramp signal when the error signal is above the maximum value of the ramp signal.

16. The circuit of claim 1 wherein the output node is coupled to a battery, and wherein the buck switching regulator charges the battery.

17. The method of claim 8 wherein the output node is coupled to a battery, and wherein the buck switching regulator charges the battery.

18. The circuit of claim 15 wherein the output node is coupled to a battery, and wherein the buck switching regulator charges the battery.