Semiconductor device and manufacturing method thereof
View Patent ↗A transistor having a multi-layer structure of oxide semiconductor layers is provided in which a second oxide semiconductor layer having a crystalline structure including indium zinc oxide is formed over a first oxide semiconductor layer having an amorphous structure, and at least a third oxide semiconductor layer is formed stacked over the second oxide semiconductor layer. The second oxide semiconductor layer mainly serves as a carrier path for the transistor. The first oxide semiconductor layer and the third oxide semiconductor layer each serve as a barrier layer for suppressing entrance of impurity states of an insulating layer in contact with the multi-layer structure to the carrier path.
1. A semiconductor device comprising:
an oxide semiconductor stack;
a first gate electrode layer comprising a region overlapping with the oxide semiconductor stack;
a first gate insulating layer between the oxide semiconductor stack and the first gate electrode layer;
a first electrode layer and a second electrode layer electrically connected to the oxide semiconductor stack;
a second gate electrode layer comprising a region overlapping with the oxide semiconductor stack; and
a second gate insulating layer between the oxide semiconductor stack and the second gate electrode layer; the oxide semiconductor stack being between the first gate insulating layer and the second gate insulating layer,
wherein the oxide semiconductor stack includes at least a first oxide semiconductor layer, a second oxide semiconductor layer comprising a crystalline structure over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer,
wherein the first oxide semiconductor layer and the third oxide semiconductor layer each include a layer expressed as InM X Zn Y O Z (X≧1, Y>1, Z>0, and M is one or more metal elements selected from Ga, Mg, Hf, Al, Sn, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), and
wherein the second oxide semiconductor layer includes an indium zinc oxide layer.
2. The semiconductor device according to claim 1 , wherein a concentration of silicon contained in the first oxide semiconductor layer or the third oxide semiconductor layer is lower than or equal to 3×10 18 /cm 3 .
3. The semiconductor device according to claim 1 , wherein a concentration of carbon contained in the first oxide semiconductor layer or the third oxide semiconductor layer is lower than or equal to 3×10 18 /cm 3 .
4. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer has a shape having an angle between a bottom surface of the second oxide semiconductor layer and a side surface of the second oxide semiconductor layer, and
wherein the angle is an acute angle.
5. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer comprises a c-axis aligned crystalline oxide semiconductor, a microcrystalline oxide semiconductor.
6. The semiconductor device according to claim 1 , wherein the second gate electrode layer overlaps with the first electrode layer and the second electrode layer.
7. The semiconductor device according to claim 1 , wherein the third oxide semiconductor layer comprises a crystalline structure over the second oxide semiconductor layer.
8. The semiconductor device according to claim 1 , wherein a degree of crystallinity of the third oxide semiconductor layer is lower than a degree of crystallinity of the second oxide semiconductor layer.
9. The semiconductor device according to claim 1 , wherein density of states of the second oxide semiconductor layer is lower than or equal to 3×10 13 /cm 3 .
10. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer on the first oxide semiconductor layer;
a third oxide semiconductor layer on the second oxide semiconductor layer, wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer;
a first electrode layer on and in contact with the third oxide semiconductor layer;
a second electrode layer on and in contact with the third oxide semiconductor layer;
a gate electrode layer comprising a region overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer;
wherein the second oxide semiconductor layer comprises a crystalline structure,
wherein the first oxide semiconductor layer and the third oxide semiconductor layer each include a layer expressed as InM X Zn Y O Z (X>1, Y>1, Z>0, and M is one or more metal elements selected from Ga, Mg, Hf, Al, Sn, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu)
wherein the second oxide semiconductor layer includes an indium zinc oxide layer.
11. The semiconductor device according to claim 10 , wherein a concentration of silicon contained in the first oxide semiconductor layer or the third oxide semiconductor layer is lower than or equal to 3×10 18 /cm 3 .
12. The semiconductor device according to claim 10 , wherein the gate electrode is located over the third oxide semiconductor layer.
13. The semiconductor device according to claim 10 , wherein the gate electrode layer overlaps with the first electrode layer and the second electrode layer.
14. The semiconductor device according to claim 10 , wherein a degree of crystallinity of the third oxide semiconductor layer is lower than a degree of crystallinity of the second oxide semiconductor layer.
15. The semiconductor device according to claim 10 , wherein density of states of the second oxide semiconductor layer is lower than or equal to 3×10 13 /cm 3 .
16. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer having tapered side surfaces;
a third oxide semiconductor layer on the second oxide semiconductor layer, wherein the third oxide semiconductor layer covers the tapered side surfaces of the second oxide semiconductor layer;
a first electrode layer on and in contact with the third oxide semiconductor layer;
a second electrode layer on and in contact with the third oxide semiconductor layer;
a gate electrode layer comprising a region overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer;
wherein the second oxide semiconductor layer comprises a crystalline structure,
wherein the first oxide semiconductor layer and the third oxide semiconductor layer each include a layer expressed as InM X Zn Y O Z (X>1, Y>1, Z>0, and M is one or more metal elements selected from Ga, Mg, Hf, Al, Sn, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu)
wherein the second oxide semiconductor layer includes an indium zinc oxide layer, and
wherein the gate electrode overlaps with the first electrode layer and the second electrode layer.
17. The semiconductor device according to claim 16 , wherein the gate electrode is located over the third oxide semiconductor layer.
18. The semiconductor device according to claim 16 , wherein a concentration of silicon contained in the first oxide semiconductor layer or the third oxide semiconductor layer is lower than or equal to 3×10 18 /cm 3 .
19. The semiconductor device according to claim 16 , wherein the second oxide semiconductor layer comprises a c-axis aligned crystalline oxide semiconductor.
20. The semiconductor device according to claim 16 , wherein a degree of crystallinity of the third oxide semiconductor layer is lower than a degree of crystallinity of the second oxide semiconductor layer.