Electro-static discharge protection circuit and liquid crystal display
View Patent ↗An electro-static discharge protection circuit for a liquid crystal display is disclosed. In response to positive electro-static charges being generated on the signal line, a thin film transistor with a gate electrode connected to the high level signal line is switched on, and the positive electro-static charges are discharged through the switched on thin film transistor. In addition, in response to negative electro-static charges being generated on the signal line, a thin film transistor with a gate electrode connected to the low level signal line is switched on, and the negative electro-static charges are discharged through the switched on thin film transistor.
1. An electro-static discharge protection circuit for a liquid crystal display, wherein the liquid crystal display is provided with a signal line, a low level signal line and a high level signal line, and the electro-static discharge protection circuit comprises:
a first thin film transistor, wherein a drain/source electrode and a source/drain electrode of the first thin film transistor are respectively connected to the signal line and the low level signal line;
a second thin film transistor, wherein a drain/source electrode and a source/drain electrode of the second thin film transistor are respectively connected to the signal line and the high level signal line;
a third thin film transistor, wherein a drain/source electrode and a source/drain electrode of the third thin film transistor are respectively connected to the signal line and the low level signal line, and a high level signal is provided to a gate electrode of the third thin film transistor; and
a fourth thin film transistor, wherein a drain/source electrode and a source/drain electrode of the fourth thin film transistor are respectively connected to the signal line and the high level signal line, and a low level signal is provided to a gate electrode of the fourth thin film transistor,
wherein when positive electro-static charges are generated on the signal line, a voltage corresponding to the positive electro-static charges is higher than a voltage of the high level signal line, a thin film transistor with a gate electrode connected to the high level signal line is switched on, and the positive electro-static charges are discharged through the switched on thin film transistor, and
when negative electro-static charges are generated on the signal line, a voltage corresponding to the negative electro-static charges is lower than a voltage of the low level signal line, a thin film transistor with a gate electrode connected to the low level signal line is switched on, and the negative electro-static charges are discharged through the switched on thin film transistor.
2. The electro-static discharge protection circuit of claim 1 , wherein the high level signal provided to the gate electrode of the third thin film transistor is provided by the high level signal line, and the low level signal provided to the gate electrode of the fourth thin film transistor is provided by the low level signal line.
3. The electro-static discharge protection circuit of claim 1 , wherein a gate electrode of the first thin film transistor is connected to the low level signal line, and a gate electrode of the second thin film transistor is connected to the high level signal line.
4. The electro-static discharge protection circuit of claim 3 , wherein the first thin film transistor is an N type thin film transistor, and the second thin film transistor is a P type thin film transistor.
5. The electro-static discharge protection circuit of claim 1 , wherein a gate electrode of the first thin film transistor is connected to the signal line, and a gate electrode of the second thin film transistor is connected to the high level signal line.
6. The electro-static discharge protection circuit of claim 5 , wherein the first thin film transistor is a P type thin film transistor, and the second thin film transistor is a P type thin film transistor.
7. The electro-static discharge protection circuit of claim 1 , wherein a gate electrode of the first thin film transistor is connected to the low level signal line, and a gate electrode of the second thin film transistor is connected to the signal line.
8. The electro-static discharge protection circuit of claim 7 , wherein the first thin film transistor is an N type thin film transistor, and the second thin film transistor is an N type thin film transistor.
9. The electro-static discharge protection circuit of claim 1 , wherein the signal line is a data line or a scanning line.
10. The electro-static discharge protection circuit of claim 1 , wherein a capacitor is arranged between the first and second thin film transistors and the third and fourth thin film transistors on the signal line.
11. A liquid crystal display, comprising an electro-static discharge protection circuit, wherein the liquid crystal display is provided with a signal line, a low level signal line and a high level signal line, and the electro-static discharge protection circuit comprises:
a first thin film transistor, wherein a drain/source electrode and a source/drain electrode of the first thin film transistor are respectively connected to the signal line and the low level signal line;
a second thin film transistor, wherein a drain/source electrode and a source/drain electrode of the second thin film transistor are respectively connected to the signal line and the high level signal line;
a third thin film transistor, wherein a drain/source electrode and a source/drain electrode of the third thin film transistor are respectively connected to the signal line and the low level signal line, and a high level signal is provided to a gate electrode of the third thin film transistor; and
a fourth thin film transistor, wherein a drain/source electrode and a source/drain electrode of the fourth thin film transistor are respectively connected to the signal line and the high level signal line, and a low level signal is provided to a gate electrode of the fourth thin film transistor,
wherein when positive electro-static charges are generated on the signal line, a voltage corresponding to the positive electro-static charges is higher than a voltage of the high level signal line, a thin film transistor with a gate electrode connected to the high level signal line is switched on, and the positive electro-static charges are discharged through the switched on thin film transistor, and
when negative electro-static charges are generated on the signal line, a voltage corresponding to the negative electro-static charges is lower than a voltage of the low level signal line, a thin film transistor with a gate electrode connected to the low level signal line is switched on, and the negative electro-static charges are discharged through the switched on thin film transistor.
12. The liquid crystal display of claim 11 , wherein the high level signal provided to the gate electrode of the third thin film transistor is provided by the high level signal line, and the low level signal provided to the gate electrode of the fourth thin film transistor is provided by the low level signal line.
13. The liquid crystal display of claim 11 , wherein a gate electrode of the first thin film transistor is connected to the low level signal line, and a gate electrode of the second thin film transistor is connected to the high level signal line.
14. The liquid crystal display of claim 13 , wherein the first thin film transistor is an N type thin film transistor, and the second thin film transistor is a P type thin film transistor.
15. The liquid crystal display of claim 11 , wherein a gate electrode of the first thin film transistor is connected to the signal line, and a gate electrode of the second thin film transistor is connected to the high level signal line.
16. The liquid crystal display of claim 15 , wherein the first thin film transistor is a P type thin film transistor, and the second thin film transistor is a P type thin film transistor.
17. The liquid crystal display of claim 11 , wherein a gate electrode of the first thin film transistor is connected to the low level signal line, and a gate electrode of the second thin film transistor is connected to the signal line.
18. The liquid crystal display of claim 17 , wherein the first thin film transistor is an N type thin film transistor, and the second thin film transistor is an N type thin film transistor.
19. The liquid crystal display of claim 11 , wherein the signal line is a data line or a scanning line.
20. The liquid crystal display of claim 11 , wherein a capacitor is arranged between the first and second thin film transistors and the third and fourth thin film transistors on the signal line.