Magnetic memory devices including shared lines
A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
1. A magnetic memory device, comprising:
a plurality of word line patterns extending in a first direction;
a plurality of bit line patterns extending in a second direction which intersects the first direction;
a plurality of source line patterns extending in the first direction, a respective one of which is disposed between a respective pair of adjacent word line patterns among the plurality of word line patterns;
a plurality of magnetic memory elements disposed below the plurality of bit line patterns; and
a plurality of metal wiring patterns extending in the first direction,
wherein a respective one of the magnetic memory elements is disposed at a respective intersection of the plurality of bit line patterns and the plurality of metal wiring patterns, when viewed in a plan view.
2. The magnetic memory device of claim 1 , further comprising:
a plurality of active regions extending in the second direction,
wherein the plurality of bit line patterns extending in the second direction are isolated from the plurality of active regions extending in the second direction.
3. The magnetic memory device of claim 1 , wherein the plurality of word line patterns extending in the first direction and the plurality of bit line patterns extending in the second direction do not intersect each other.
4. The magnetic memory device of claim 3 , wherein the plurality of source line patterns extending in the first direction and the plurality of bit line patterns extending in the second direction do not intersect each other.
5. The magnetic memory device of claim 1 , further comprising:
a plurality of active regions,
wherein the plurality of magnetic memory elements are disposed side-by-side on either side of the plurality of active regions, and
wherein the plurality of word line patterns extending in the first direction and the plurality of source line patterns extending in the first direction intersect the plurality of bit line patterns extending in the second direction.
6. A magnetic memory device, comprising:
first and second metal wiring patterns extending in a first direction;
a plurality of bit lines extending in a second direction and intersecting the first and second metal wiring patterns;
a plurality of magnetic memory elements, a respective one of which is disposed at a respective intersection of the first and second metal wiring patterns and the plurality of bit lines when viewed in a plan view;
first and second word lines extending in the first direction;
a source line extending in the first direction between the first and second metal wiring patterns;
first selection field effect transistor (FET), a drain of which is connected to the first metal wiring pattern, a source of which is connected to the source line and a gate of which is connected to the first word line; and
a second selection FET, a drain of which is connected to the second metal wiring pattern, a source of which is connected to the source line and a gate of which is connected to the second word line.
7. The magnetic memory device of claim 6 wherein the first word line is between the first metal wiring pattern and the source line, and the second word line is between the second metal wiring pattern and the source line.
8. The magnetic memory device of claim 7 wherein the first and second selection FETs are offset from the plurality of magnetic memory elements in the first direction.
9. The magnetic memory device of claim 6 wherein the first and second word lines intersect the plurality of bit lines.
10. The magnetic memory device of claim 9 wherein the source line intersects the plurality of bit lines.