Semiconductor device and structure

1. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,

wherein said first layer comprises a first clock distribution structure,

wherein said second layer comprises a second clock distribution structure,

wherein said second clock distribution structure is connected to said first clock distribution structure with a plurality of through layer vias, and

wherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.

2. A 3D device according to claim 1 ,

wherein at least one of said through layer vias (TLV) has a diameter of less than 400 nm.

3. A 3D device according to claim 1 , further comprising:

a heat spreader layer disposed between said first layer and said second layer.

4. A 3D device according to claim 1 , further comprising:

a heat removal path between said second transistors and an external surface of said device.

5. A 3D device according to claim 1 , further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path from said second transistors to an external surface of said device.

6. A 3D device according to claim 1 ,

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain, and

wherein said second layer comprises a plurality of second flip-flops connected to form a second scan chain.

7. A 3D device according to claim 1 ,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units, and

wherein said first bus and said second bus are interconnected so said second logic units could communicate through said first bus with at least one of said first logic units.

8. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,

wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain,

wherein said second layer comprises a plurality of second flip-flops connected to form a second scan chain, and

wherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.

9. A 3D device according to claim 8 , further comprising:

a plurality of through layer vias as part of connection paths between said first transistors and said second transistors,

wherein at least one of said through layer vias has a diameter of less than 400 nm.

10. A 3D device according to claim 8 and further comprising:

a heat spreader layer disposed between said first layer and said second layer.

11. A 3D device according to claim 8 , further comprising:

a heat removal path between said second transistors and an external surface of said device.

12. A 3D device according to claim 8 , further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path from said second transistors to an external surface of said device.

13. A 3D device according to claim 8 ,

wherein said first layer comprises a first clock distribution structure,

wherein said second layer comprises a second clock distribution structure and wherein said second clock distribution structure is connected to said first clock distribution structure.

14. A 3D device, comprising:

a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;

a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,

wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,

wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units,

wherein said first bus and said second bus are interconnected,

wherein said interconnected comprise through layer vias, and

wherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.

15. A 3D device according to claim 14 ,

wherein said second layer thickness is less than 1 micrometer.

16. A 3D device according to claim 14 ,

wherein at least one of said second logic units has a plurality of connections to an external component.

17. A 3D device according to claim 14 , wherein said second bus is one of the following:

i.) an Advanced Microcontroller Bus Architecture (AMBA) bus;

ii) a CoreConnect bus;

iii) a STBus;

iv.) a Wishbone bus;

v.) an Open Core Protocol (OCP) bus, or

vi.) a Virtual Component Interface (VCI) bus.

18. A 3D device according to claim 14 ,

wherein said first layer comprises a first clock distribution structure, said first clock distribution structure comprises a first clock origin,

wherein said second layer comprises a second clock distribution structure,

wherein said second clock distribution structure is connected to first clock distribution structure.

19. A 3D device according to claim 14 , further comprising:

a heat spreader layer disposed between said first layer and said second layer.

20. A 3D device according to claim 14 , further comprising:

a heat removal path between said second transistors and an external surface of said device.