High performance standard cell with continuous oxide definition and characterized leakage current
A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.
1. A cell comprising:
a continuous oxide definition (OD) region defined in a substrate;
a gate for a transistor between a first dummy gate and a second dummy gate, wherein a source for the transistor is defined in a first portion of the continuous OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a second portion of the continuous OD region between the gate and a first side of the second dummy gate;
a first gate-directed local interconnect coupled to a third portion of the continuous OD region adjacent a second opposing side of the second dummy gate;
a first diffusion-directed local interconnect configured to couple the first gate-directed local interconnect to the second dummy gate; and
a first via configured to couple the first diffusion-directed local interconnect to a source voltage interconnect in a metal layer adjacent the substrate.
2. The cell of claim 1 , further comprising:
a second gate-directed local interconnect configured to couple to the first portion of the continuous OD region defining the source; and
a second diffusion-directed local interconnect configured to couple the first dummy gate to the second gate-directed local interconnect.
3. The cell of claim 2 , further comprising a second via configured to couple the second gate-directed local interconnect to a source voltage interconnect in a metal layer adjacent the substrate.
4. The cell of claim 2 , wherein the first gate-directed local interconnect and the first diffusion-directed local interconnect are each level 2 local interconnects, the cell further comprising a first level 1 gate-directed local interconnect arranged between the first level 2 gate-directed local interconnect and the third portion of the continuous OD region to couple the first level 2 gate-directed local interconnect to the third portion of the continuous OD region, and wherein the first via is a level 3 local interconnect.
5. The cell of claim 4 , wherein the first level 1 gate-directed local interconnect, the first level 2 gate-directed local interconnect, and the first level 2 diffusion-directed local interconnect all comprise tungsten.
6. The cell of claim 4 , wherein the first dummy gate, the gate, and the second dummy gate are separated from each other according to a gate pitch.
7. The cell of claim 6 , wherein the gate comprises a plurality of gates.
8. The cell of claim 1 , wherein the cell is a last cell in an array of cells extending across the continuous OD region, and wherein the continuous OD region extends from a first end to an opposing second end adjacent the third portion of the continuous OD region.
9. The cell of claim 1 , wherein the cell is a first cell in an array of cells extending across the continuous OD region, and wherein the continuous OD region extends from a first end adjacent the third portion of the continuous OD region to an opposing second end.
10. The cell of claim 1 , further comprising an additional continuous OD region.
11. The cell of claim 1 , wherein the cell includes a plurality of transistors.
12. The cell of claim 1 , wherein the continuous OD region comprises a PMOS continuous OD region.
13. The cell of claim 1 , wherein the continuous OD region comprises an NMOS continuous OD region.
14. A method for forming a cell, comprising:
forming a continuous oxide definition (OD) region defined in a substrate;
forming a gate for a transistor arranged according to a gate pitch between a first dummy gate and a second dummy gate, wherein a source for the transistor is defined in a portion of the continuous OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a portion of the continuous OD region between the gate and a first side of the second dummy gate;
forming a first gate-directed local interconnect coupled to a portion of the continuous OD region adjacent a second opposing side of the second dummy gate;
forming a first diffusion-directed local interconnect configured to couple the first gate-directed local interconnect to the second dummy gate; and
forming a via configured to couple the first gate-directed local interconnect to a source voltage supply.