IP Library › Granted Patent US 9,318,571
Granted Patent B2
US 9,318,571 · App. 12/391,213 · Granted Apr 19, 2016

Gate structure and method for trimming spacers

Inventors: I-Chang Wang (Tainan, TW); Ming-Tsung Chen (Hsin-Chu Hsien, TW); Ling-Chun Chou (Yunlin County, TW); Po-Chao Tsao (Taipei Hsien, TW); Tsung-Hung Chang (Yunlin County, TW); Hui-Ling Chen (Kao-Hsiung Hsien, TW); Cheng-Yen Wu (Kaohsiung, TW); Chieh-Te Chen (Kaohsiung, TW); Shin-Chi Chen (Tainan County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/4983H01L29/6653H01L29/6656
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Quick Facts
Patent No.
US 9,318,571
App. No.
12/391,213
Granted
Apr 19, 2016
Kind
B2
Abstract

A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.

Claims (17)

1. A gate structure, comprising:

a gate disposed on a substrate;

a first spacer disposed on said substrate, surrounding said gate and being in an L shape;

a second spacer disposed on said first spacer and surrounding said gate and having an arc outer sidewall, said second spacer being lower than half of said first spacer, wherein said arc outer sidewall has two ends contacting a horizontal part and a vertical part of said L shape of said first spacer respectively, an outer sidewall of a bottom of said first spacer and said arc outer sidewall of a bottom of said second spacer align with each other, and a top of said first spacer and a top of said second spacer have discontinuous change; and

a stress film disposed on said gate, wherein said stress film directly contacts to said substrate, said two ends of said arc outer sidewall, and said vertical part of said L shape of said first spacer.

2. The gate structure of claim 1 , further comprising:

a liner disposed between said gate and said first spacer, having a nitride or an oxide.

3. The gate structure of claim 1 , wherein said first spacer and said second spacer have etching selectivity.

4. The gate structure of claim 1 , wherein said second spacer is lower than said first spacer to expose said vertical part of said L shape of said first spacer.

5. The gate structure of claim 1 , wherein said gate structure has only said first spacer and said second spacer.

6. A gate structure, comprising:

a gate disposed on a substrate;

a first spacer disposed on said substrate, surrounding said gate and being in an L shape;

a second spacer disposed on said first spacer and surrounding said gate and in a L shape, said second spacer being lower than half of said first spacer, wherein an outer sidewall of a bottom of said first spacer and an outer sidewall of a bottom of said second spacer align with each other, and a top of said first spacer and a top of said second spacer have discontinuous change; and

a third spacer disposed on said second spacer and surrounding said gate.

7. The gate structure of claim 6 , wherein said third spacer and said second spacer have etching selectivity and said third spacer comprises an oxide or a nitride.

8. The gate structure of claim 6 , wherein said second spacer is lower than both said first spacer and said third spacer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2009
From: WANG, I-CHANG; CHEN, MING-TSUNG; CHOU, LING-CHUN; TSAO, PO-CHAO; CHANG, TSUNG-HUNG; CHEN, HUI-LING; WU, CHENG-YEN; CHEN, CHIEH-TE; CHEN, SHIN-CHI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 022298/0563 →
Continuity (1)
Related Publication 20100213554A1 · Aug 26, 2010