III-V semiconductor device having self-aligned contacts
A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
1. A structure comprising:
a gate conductor partially embedded in a III-V compound semiconductor-containing heterostructure, the gate conductor extending from above the III-V compound semiconductor-containing heterostructure down into the III-V compound semiconductor-containing heterostructure;
a pair of inner spacers positioned along a vertical sidewall of the gate conductor between the gate conductor and the III-V compound semiconductor-containing heterostructure;
a pair of outer spacers adjacent to the pair of inner spacers above the III-V compound semiconductor-containing heterostructure, the outer spacers are in direct contact with and self-aligned to the inner spacers; and
a pair of source-drain contacts positioned within the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
2. The structure of claim 1 , wherein the III-V compound semiconductor-containing heterostructure comprises:
a III-V compound semiconductor buffer layer on an upper surface of a substrate;
a III-V compound semiconductor channel layer on an upper surface of the III-V compound semiconductor buffer layer;
a III-V compound semiconductor barrier layer on an upper surface of the III-V compound semiconductor channel layer; and
a III-V compound semiconductor cap layer on an upper surface of the III-V compound semiconductor barrier layer.
3. The structure of claim 1 , wherein the pair of source-drain contacts are positioned in an uppermost layer of the III-V compound semiconductor-containing heterostructure.
4. The structure of claim 1 , wherein the gate conductor extends from above the III-V compound semiconductor-containing heterostructure down to a channel layer within the III-V compound semiconductor-containing heterostructure.
5. The structure of claim 1 , wherein the gate conductor extends from above the III-V compound semiconductor-containing heterostructure down to a barrier layer within the III-V compound semiconductor-containing heterostructure.
6. The structure of claim 1 , further comprising:
a gate dielectric positioned along a bottom and opposite sides of the gate conductor, the gate dielectric located between the gate conductor and the III-V compound semiconductor-containing heterostructure.
7. The structure of claim 1 , further comprising:
an isolation region separating the gate conductor and the source-drain contacts from an adjacent gate conductor or an adjacent source-drain contact; and
a pair of parasitic spacers in direct contact with and self-aligned to the isolation region.