IP Library › Granted Patent US 9,324,856
Granted Patent B2
US 9,324,856 · App. 14/291,967 · Granted Apr 26, 2016

MOSFET having dual-gate cells with an integrated channel diode

Inventors: Christopher Boguslaw Kocon (Mountain Top, PA); John Manning Savidge Neilson (Norristown, PA)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L29/7803H01L23/50H01L27/0629H01L29/1095H01L29/404H01L29/407H01L29/4236H01L29/42356H01L29/7811H01L29/7813H01L29/861
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,324,856
App. No.
14/291,967
Granted
Apr 26, 2016
Kind
B2
Abstract

A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

Claims (20)

1. A semiconductor device, comprising:

a substrate;

a metal oxide semiconductor field effect transistor (MOSFET) cell including:

a drift region of a first conductivity type in the substrate;

active trenches formed adjacent to said drift region, said active trenches including an electrically conductive filler material surrounded by a trench dielectric liner;

a split gate comprising a MOS gate and a diode gate over said drift region and between said active trenches, said split gate using said active trenches as field plates;

a body region of a second conductivity type opposite from said first conductivity type abutting said active trenches, and the body region including a first body region proximate to said MOS gate and a second body region proximate to said diode gate;

a source region of said first conductivity type formed in said body region, the source region including a first source portion proximate to said MOS gate and a second source portion proximate to said diode gate;

a drain contact formed on a bottom side of said substrate opposing from the split gate, and

a connector connecting said diode gate to said second source portion to form a channel diode integrated to a MOSFET controlled by said MOS gate, wherein said MOS gate is electrically isolated from said first source portion.

2. The semiconductor device of claim 1 , wherein said second body region is lighter in doping by at least a factor of two (2) as compared to said first body region.

3. The semiconductor device of claim 1 , further comprising a termination trench abutting at least two vertical sides of said MOSFET cell.

4. The semiconductor device of claim 1 , wherein said connector comprises a metal.

5. The semiconductor device of claim 1 , wherein said connector comprises doped polysilicon.

6. The semiconductor device of claim 1 , wherein said substrate comprises silicon.

7. The semiconductor device of claim 1 , further comprising a first bus connecting said MOS gate of said MOSFET cell and a second bus connecting said diode gate of said MOSFET cell and to said second source portion.

8. The semiconductor device of claim 1 , wherein said MOS gate is configured as a MOS gate stripe and said diode gate is configured as a diode gate stripe, wherein said active trenches are aligned in parallel with said MOS gate stripe and said diode gate stripe.

9. The semiconductor device of claim 1 , wherein said MOS gate is configured as a MOS gate stripe and said diode gate is configured as a diode gate stripe, wherein said active trenches are aligned perpendicular to said MOS gate stripe and said diode gate stripe.

10. The semiconductor device of claim 1 , wherein said active trenches comprise active trench wells.

11. The semiconductor device of claim 1 , wherein said active trenches each includes an upper portion adjacent to a top surface of the substrate and a lower portion below the upper portion such that the upper portion is wider than the lower portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2014
From: KOCON, CHRISTOPHER BOGUSLAW; NEILSON, JOHN MANNING SAVIDGE
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 032999/0343 →
Continuity (1)
Related Publication 20150349110A1 · Dec 3, 2015