Method of driving a display panel and display apparatus for performing the same

1. A method of driving a display panel, comprising:

determining whether a driving mode is a two-dimensional image mode or a three-dimensional image mode;

generating a first gate driving control signal and a second gate driving control signal by converting an input control signal inputted in accordance with the driving mode;

outputting a first gate signal to an odd-numbered gate line connected to a first sub-pixel within a unit pixel of the display panel based on the first gate driving control signal; and

outputting a second gate signal to an even-numbered gate line connected to a second sub-pixel within the unit pixel of the display panel based on the second gate driving control signal,

wherein the odd-numbered gate line and the even numbered gate line adjacent to the odd-numbered gate line have a different activation time in a two-dimensional image mode and the odd-numbered gate line and the even numbered gate line adjacent to the odd-numbered gate line have a same activation time in a three-dimensional image mode irrespective of a frame frequency, and

wherein a frame of the three-dimensional image mode is shorter than a frame of the two-dimensional image mode, the frame being time of scanning all gate lines.

2. The method of claim 1 , wherein the first sub-pixel is a high pixel and the second sub-pixel is a low pixel having a lower pixel voltage than the high pixel.

3. The method of claim 2 , wherein a first odd-numbered gate line and a first even numbered gate line adjacent to the first odd-numbered gate line have a first activation time, and a second odd-numbered gate line adjacent to the first even-numbered gate line and a second even numbered gate line adjacent to the second odd-numbered gate line have a second activation time having one interval delay in the three-dimensional image mode.

4. The method of claim 3 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

5. The method of claim 2 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

6. The method of claim 1 , wherein a first odd-numbered gate line and a first even numbered gate line adjacent to the first odd-numbered gate line have a first activation time, and a second odd-numbered gate line adjacent to the first even-numbered gate line and a second even numbered gate line adjacent to the second odd-numbered gate line have a second activation time having one interval delay in the three-dimensional image mode.

7. The method of claim 6 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

8. The method of claim 1 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

9. A method of driving a display panel, comprising:

determining whether a driving mode is a two-dimensional image mode or a three-dimensional image mode;

generating a first gate driving control signal and a second gate driving control signal by converting an input control signal inputted in accordance with the driving mode;

outputting a first gate signal to an odd-numbered gate line connected to a first sub-pixel and a second sub-pixel based on the first gate driving control signal; and

outputting a second gate signal to an even-numbered gate line connected to a first sub-pixel and a second sub-pixel based on the second gate driving control signal,

wherein the odd-numbered gate line and the even numbered gate line adjacent to the odd-numbered gate line have a different activation time in a two-dimensional image mode, and the odd-numbered gate line and the even numbered gate line adjacent to the odd-numbered gate line have a same activation time in a three-dimensional image mode irrespective of a frame frequency, and

wherein a frame of the three-dimensional image mode is shorter than a frame of the two-dimensional image mode, the frame being time of scanning all gate lines.

10. The method of claim 9 , wherein the first sub-pixel is a high pixel and the second sub-pixel is a low pixel having a lower pixel voltage than the high pixel.

11. The method of claim 10 , wherein a first odd-numbered gate line and a first even numbered gate line adjacent to the first odd-numbered gate line have a first activation time, and a second odd-numbered gate line adjacent to the first even-numbered gate line and a second even numbered gate line adjacent to the second odd-numbered gate line have a second activation time having one interval delay in the three-dimensional image mode.

12. The method of claim 11 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

13. The method of claim 10 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

14. The method of claim 9 , wherein a first odd-numbered gate line and a first even numbered gate line adjacent to the first odd-numbered gate line have a first activation time, and a second odd-numbered gate line adjacent to the first even-numbered gate line and a second even numbered gate line adjacent to the second odd-numbered gate line have a second activation time having one interval delay in the three-dimensional image mode.

15. The method of claim 14 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

16. The method of claim 9 , further comprising supplying the first gate driving control signal and the second driving control signal to a first gate driving part and a second gate driving part, respectively.

17. A display apparatus comprising:

a display panel comprising a plurality of unit pixels comprising a first sub-pixel and a second sub-pixel;

a timing controller determining whether a driving mode is a two-dimensional image mode or a three-dimensional image mode, and generating a first gate driving control signal and a second gate driving control signal by converting an input control signal inputted in accordance with the driving mode;

a first gate driving part outputting a first gate signal to an odd-numbered gate line; and

a second gate driving part outputting a second gate signal to an even-numbered gate line,

wherein the first gate signal and the second gate signal have a different activation time in a two-dimensional image mode and the first gate signal and the second gate signal adjacent to the first gate signal have a same activation time in a three-dimensional image mode irrespective of a frame frequency, and

wherein a frame of the three-dimensional image mode is shorter than a frame of the two-dimensional image mode, the frame being time of scanning all gate lines.

18. The display apparatus of claim 17 , wherein an N-th even gate line is disposed between an n-th odd gate line and an (n+1)-th odd gate line (‘n’ is a natural number), and

the first gate signal or the second gate signal is sequentially outputted to the n-th odd gate line, the n-th even gate line and the (n+1)-th odd gate line in the two-dimensional image mode.

19. The display apparatus of claim 18 , wherein a first voltage is charged in the first sub-pixel, and a second voltage lower than the first voltage is charged in the second sub-pixel.

20. The display apparatus of claim 17 , wherein an n-th even gate line is disposed between an n-th odd gate line and an (n+1)-th odd gate line (‘n’ is a natural number) in the 2D image mode, and

the first gate signal or the second gate signal is simultaneously outputted to the n-th even gate line and the N-th odd gate line in the three-dimensional image mode.

21. The display apparatus of claim 20 , wherein a third voltage is charged in the first and the second sub-pixels.

22. The display apparatus of claim 17 , wherein each of the first sub-pixel and the second sub-pixel in the unit pixels in a same column is connected to different gate lines and a same data line.

23. The display apparatus of claim 22 , wherein the first sub-pixel comprises a first switching element, a first liquid crystal capacitor connected to the first switching element and a first storage capacitor connected to the first switching element,

the second sub-pixel comprises a second switching element, a second liquid crystal capacitor connected to the second switching element and a first storage capacitor connected to the second switching element,

the first switching element is connected to an odd-numbered gate line, and

the second switching element is connected to an even-numbered gate line.

24. The display apparatus of claim 17 , wherein each of the first sub-pixel and the second sub-pixel in the unit pixels in a same row is connected to a same gate line and the different data lines.

25. The display apparatus of claim 24 , wherein each of the unit pixels comprises:

a first unit pixel connected to a first gate line, a first data line and a second data line adjacent to the first data line;

a second unit pixel connected to a second gate line adjacent to the first gate line, a third data line adjacent to the second data line and a fourth data line adjacent to the third data line;

a third unit pixel connected to the first gate line, the third data line and the fourth data line; and

a fourth unit pixel connected to the second gate line, the first data line and the second data line, and

wherein a switching element of the first sub-pixel of the first unit pixel is connected to the first gate line and the first data line, and

a switching element of the first sub-pixel of the third unit pixel is connected to the first gate line and the fourth data line.

26. The display apparatus of claim 25 , wherein a switching element of the second sub-pixel of the first unit pixel is connected to the first gate line and the second data line, and

a switching element of the second sub-pixel of the third unit pixel is connected to the first gate line and the third data line.

27. The display apparatus of claim 25 , wherein a switching element of the first sub-pixel of the second unit pixel is connected to the second gate line and the third data line, and

a switching element of the first sub-pixel of the fourth unit pixel is connected to the second gate line and the second data line.

28. The display apparatus of claim 25 , wherein a switching element of the second sub-pixel of the second unit pixel is connected to the second gate line and the fourth data line, and

a switching element of the second sub-pixel of the fourth unit pixel is connected to the second gate line and the first data line.

29. The display apparatus of claim 24 , wherein each of the unit pixels comprises:

a first unit pixel connected to a first gate line, a first data line and a second data line adjacent to the first data line;

a second unit pixel connected to a second gate line adjacent to the first gate line, a third data line adjacent to the second data line and a fourth data line adjacent to the third data line;

a third unit pixel connected to the first gate line, the third data line and the fourth data line; and

a fourth unit pixel connected to the second gate line, the first data line and the second data line, and

wherein a switching element of the first sub-pixel of the first unit pixel is connected to the first gate line and the first data line, and

a switching element of the first sub-pixel of the third unit pixel is connected to the first gate line and the third data line.

30. The display apparatus of claim 29 , wherein a switching element of the second sub-pixel of the first unit pixel is connected to the first gate line and the second data line, and

a switching element of the second sub-pixel of the third unit pixel is connected to the first gate line and the fourth data line.

31. The display apparatus of claim 29 , wherein a switching element of the first sub-pixel of the second unit pixel is connected to the second gate line and the third data line, and

a switching element of the first sub-pixel of the fourth unit pixel is connected to the second gate line and the first data line.

32. The display apparatus of claim 31 , wherein a switching element of the second sub-pixel of the second unit pixel is connected to the second gate line and the fourth data line, and

a switching element of the second sub-pixel of the fourth unit pixel is connected to the second gate line and the second data line.