Granted Patent B2

US 9,336,180 · App. 13/874,838 · Granted May 10, 2016

Inventor: Mark John Ebersole (Cedar Park, TX)

Assignee: VIA TECHNOLOGIES, INC.

G06F15/7842G06F9/3017G06F9/30076G06F9/30112G06F9/30138G06F9/30174G06F9/30189G06F9/30196G06F9/4401

Abstract

Claims (128)

1. A microprocessor, comprising:

hardware registers that instantiate the IA-32 Architecture EDX and EAX general purpose registers (GPRs); and

hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs;

wherein the microprocessor associates with each of the R8-R15 GPRs a respective unique Model Specific Register (MSR) address;

wherein in response to an IA-32 Architecture Read from Model Specific Register (RDMSR) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers.

2. The microprocessor of claim 1 ,

wherein the microprocessor is programmable to operate in a plurality of operating modes that include an Intel 64 Architecture 64-bit operating mode and non-64-bit operating modes;

wherein, in response to the RDMSR instruction, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers, even when the microprocessor is operating in one of the non-64-bit operating modes.

3. The microprocessor of claim 2 , wherein the R8-R15 GPRs are accessible by the Intel 64 Architecture Move Quadword (MOVQ) instruction only when the microprocessor is operating in the Intel 64 Architecture 64-bit operating mode.

4. The microprocessor of claim 1 , further comprising:

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within an MSR address space defined by the microprocessor;

wherein the microprocessor obtains the respective unique MSR address of the one of the R8-R15 GPRs from the IA-32 Architecture ECX GPR.

5. The microprocessor of claim 1 , further comprising:

wherein the microprocessor defines a unique GPR MSR address within an MSR address space defined by the microprocessor, wherein the unique GPR MSR address is associated globally with a set of GPRs of the microprocessor that includes the R8-R15 GPRs;

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within a GPR MSR sub-address space defined by the microprocessor;

wherein when the IA-32 Architecture ECX GPR contains the globally associated unique MSR address, the microprocessor obtains the respective unique MSR address of the one of the R8-R15 GPRs from a predetermined one of the IA-32 Architecture EAX, EBX, EDX, EBP, ESP, ESI and EDI GPRs.

6. The microprocessor of claim 1 , further comprising:

hardware registers that instantiate the Intel 64 Architecture RAX-RSP GPRs;

wherein the microprocessor associates with each of the RAX-RSP GPRs a respective unique MSR address;

wherein in response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the RAX-RSP GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the RAX-RSP GPRs into the hardware registers that instantiate the EDX:EAX registers.

7. The microprocessor of claim 1 , further comprising:

hardware registers that instantiate the Streaming SIMD Extensions (SSE) XMM registers;

wherein the microprocessor associates with each 64-bit half of the XMM registers a respective unique MSR address;

wherein in response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of a 64-bit half of one of the XMM registers, the microprocessor reads the contents of the hardware register that instantiates the specified 64-bit half of the one of the XMM registers into the hardware registers that instantiate the EDX:EAX registers.

8. The microprocessor of claim 7 ,

wherein, in response to the RDMSR instruction, the microprocessor reads the contents of the hardware register that instantiates the specified 64-bit half of the one of the XMM registers into the hardware registers that instantiate the EDX:EAX registers, even when SSE state support is not enabled on the microprocessor.

9. The microprocessor of claim 1 , further comprising:

hardware registers that instantiate the Advanced Vector Extensions (AVX) YMM registers;

wherein the microprocessor associates with each 64-bit quarter of the YMM registers a respective unique MSR address;

wherein in response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of a 64-bit quarter of one of the YMM registers, the microprocessor reads the contents of the hardware register that instantiates the specified 64-bit quarter of the one of the YMM registers into the hardware registers that instantiate the EDX:EAX registers.

10. The microprocessor of claim 9 ,

wherein, in response to the RDMSR instruction, the microprocessor reads the contents of the hardware register that instantiates the specified 64-bit quarter of the one of the YMM registers into the hardware registers that instantiate the EDX:EAX registers, even when YMM state support is not enabled on the microprocessor.

11. The microprocessor of claim 1 , wherein in response to an IA-32 Architecture Read from Performance-Monitoring Counters (RDPMC) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers.

12. A method for operation of a microprocessor having hardware registers that instantiate the IA-32 Architecture EDX and EAX general purpose registers (GPRs) and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs, the method comprising:

associating, by the microprocessor, with each of the R8-R15 GPRs a respective unique Model Specific Register (MSR) address;

encountering, by the microprocessor, an IA-32 Architecture Read from Model Specific Register (RDMSR) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs; and

reading, by the microprocessor, the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers.

13. The method of claim 12 ,

wherein the microprocessor is programmable to operate in a plurality of operating modes that include an Intel 64 Architecture 64-bit operating mode and non-64-bit operating modes;

wherein said reading the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers is performed by the microprocessor even when the microprocessor is operating in one of the non-64-bit operating modes.

14. The method of claim 12 ,

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within an MSR address space defined by the microprocessor;

wherein the method further comprises:

obtaining, by the microprocessor, the respective unique MSR address of the one of the R8-R15 GPRs from the IA-32 Architecture ECX GPR.

15. The method of claim 12 ,

wherein the microprocessor defines a unique GPR MSR address within an MSR address space defined by the microprocessor, wherein the unique GPR MSR address is associated globally with a set of GPRs of the microprocessor that includes the R8-R15 GPRs;

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within a GPR MSR sub-address space defined by the microprocessor;

the method further comprising:

obtaining, by the microprocessor when the IA-32 Architecture ECX GPR contains the globally associated unique MSR address, the respective unique MSR address of the one of the R8-R15 GPRs from a predetermined one of the IA-32 Architecture EAX, EBX, EDX, EBP, ESP, ESI and EDI GPRs.

16. The method of claim 12 ,

wherein the microprocessor also includes hardware registers that instantiate the Intel 64 Architecture RAX-RSP GPRs;

wherein the microprocessor associates with each of the RAX-RSP GPRs a respective unique MSR address;

the method further comprising:

reading, by the microprocessor in response to encountering an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the RAX-RSP GPRs, the contents of the hardware register that instantiates the specified one of the RAX-RSP GPRs into the hardware registers that instantiate the EDX:EAX registers.

17. The method of claim 12 ,

wherein the microprocessor also includes hardware registers that instantiate the Streaming SIMD Extensions (SSE) XMM registers;

wherein the microprocessor associates with each 64-bit half of the XMM registers a respective unique MSR address;

the method further comprising:

reading, by the microprocessor in response to encountering an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of a 64-bit half of one of the XMM registers, the contents of the hardware register that instantiates the specified 64-bit half of the one of the XMM registers into the hardware registers that instantiate the EDX:EAX registers.

18. The method of claim 12 ,

wherein the microprocessor also includes hardware registers that instantiate the Advanced Vector Extensions (AVX) YMM registers;

wherein the microprocessor associates with each 64-bit quarter of the YMM registers a respective unique MSR address;

the method further comprising:

reading, by the microprocessor in response to encountering an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of a 64-bit quarter of one of the YMM registers, the contents of the hardware register that instantiates the specified 64-bit quarter of the one of the YMM registers into the hardware registers that instantiate the EDX:EAX registers.

19. A microprocessor, comprising:

hardware registers that instantiate the IA-32 Architecture EDX and EAX general purpose registers (GPRs); and

hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs;

wherein the microprocessor associates with each of the R8-R15 GPRs a respective unique Model Specific Register (MSR) address;

wherein in response to an IA-32 Architecture Write to Model Specific Register (WRMSR) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers.

20. The microprocessor of claim 19 ,

wherein the microprocessor is programmable to operate in a plurality of operating modes that include an Intel 64 Architecture 64-bit operating mode and non-64-bit operating modes;

wherein, in response to the WRMSR instruction, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers, even when the microprocessor is operating in one of the non-64-bit operating modes.

21. The microprocessor of claim 20 , wherein the R8-R15 GPRs are accessible by the Intel 64 Architecture Move Quadword (MOVQ) instruction only when the microprocessor is operating in the Intel 64 Architecture 64-bit operating mode.

22. The microprocessor of claim 19 , further comprising:

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within an MSR address space defined by the microprocessor;

wherein the microprocessor obtains the respective unique MSR address of the one of the R8-R15 GPRs from the IA-32 Architecture ECX GPR.

23. The microprocessor of claim 19 , further comprising:

wherein the microprocessor defines a unique GPR MSR address within an MSR address space defined by the microprocessor, wherein the unique GPR MSR address is associated globally with a set of GPRs of the microprocessor that includes the R8-R15 GPRs;

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within a GPR MSR sub-address space defined by the microprocessor;

wherein when the IA-32 Architecture ECX GPR contains the globally associated unique MSR address, the microprocessor obtains the respective unique MSR address of the one of the R8-R15 GPRs from a predetermined one of the IA-32 Architecture EAX, EBX, EDX, EBP, ESP, ESI, and EDI GPRs.

24. The microprocessor of claim 19 , further comprising:

hardware registers that instantiate the Intel 64 Architecture RAX-RSP GPRs;

wherein the microprocessor associates with each of the RAX-RSP GPRs a respective unique MSR address;

wherein in response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the RAX-RSP GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the RAX-RSP GPRs the contents of the hardware registers that instantiate the EDX:EAX registers.

25. The microprocessor of claim 19 , further comprising:

hardware registers that instantiate the Streaming SIMD Extensions (SSE) XMM registers;

wherein the microprocessor associates with each 64-bit half of the XMM registers a respective unique MSR address;

wherein in response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of a 64-bit half of one of the XMM registers, the microprocessor writes into the hardware register that instantiates the specified 64-bit half of the one of the XMM registers the contents of the hardware registers that instantiate the EDX:EAX registers.

26. The microprocessor of claim 25 ,

wherein, in response to the WRMSR instruction, the microprocessor writes into the hardware register that instantiates the specified 64-bit half of the one of the XMM registers the contents of the hardware registers that instantiate the EDX:EAX registers, even when SSE state support is not enabled on the microprocessor.

27. The microprocessor of claim 19 , further comprising:

hardware registers that instantiate the Advanced Vector Extensions (AVX) YMM registers;

wherein the microprocessor associates with each 64-bit quarter of the YMM registers a respective unique MSR address;

wherein in response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of a 64-bit quarter of one of the YMM registers, the microprocessor writes into the hardware register that instantiates the specified 64-bit quarter of the one of the YMM registers the contents of the hardware registers that instantiate the EDX:EAX registers.

28. The microprocessor of claim 27 ,

wherein, in response to the WRMSR instruction, the microprocessor writes into the hardware register that instantiates the specified 64-bit quarter of the one of the YMM registers the contents of the hardware registers that instantiate the EDX:EAX registers, even when YMM state support is not enabled on the microprocessor.

29. A method for operation of a microprocessor having hardware registers that instantiate the IA-32 Architecture EDX and EAX general purpose registers (GPRs) and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs, the method comprising:

associating, by the microprocessor, with each of the R8-R15 GPRs a respective unique Model Specific Register (MSR) address;

encountering, by the microprocessor, an IA-32 Architecture Write to Model Specific Register (WRMSR) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs;

writing, by the microprocessor, into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers.

30. The method of claim 29 ,

wherein the microprocessor is programmable to operate in a plurality of operating modes that include an Intel 64 Architecture 64-bit operating mode and non-64-bit operating modes;

wherein said writing into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers is performed by the microprocessor even when the microprocessor is operating in one of the non-64-bit operating modes.

31. The method of claim 29 ,

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within an MSR address space defined by the microprocessor;

the method further comprising:

obtaining, by the microprocessor, the respective unique MSR address of the one of the R8-R15 GPRs from the IA-32 Architecture ECX GPR.

32. The method of claim 29 ,

wherein the microprocessor defines a unique GPR MSR address within an MSR address space defined by the microprocessor, wherein the unique GPR MSR address is associated globally with a set of GPRs of the microprocessor that includes the R8-R15 GPRs;

wherein the respective unique MSR address associated with each of the R8-R15 GPRs is a respective unique value within a GPR MSR sub-address space defined by the microprocessor;

the method further comprising:

obtaining, by the microprocessor when the IA-32 Architecture ECX GPR contains the globally associated unique MSR address, the respective unique MSR address of the one of the R8-R15 GPRs from a predetermined one of the IA-32 Architecture EAX, EBX, EDX, EBP, ESP, ESI and EDI GPRs.

33. The method of claim 29 ,

wherein the microprocessor also includes hardware registers that instantiate the Intel 64 Architecture RAX-RSP GPRs;

wherein the microprocessor associates with each of the RAX-RSP GPRs a respective unique MSR address;

the method further comprising:

writing, by the microprocessor in response to encountering an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the RAX-RSP GPRs, into the hardware register that instantiates the specified one of the RAX-RSP GPRs the contents of the hardware registers that instantiate the EDX:EAX registers.

34. The method of claim 29 ,

wherein the microprocessor also includes hardware registers that instantiate the Streaming SIMD Extensions (SSE) XMM registers;

wherein the microprocessor associates with each 64-bit half of the XMM registers a respective unique MSR address;

the method further comprising:

writing, by the microprocessor in response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of a 64-bit half of one of the XMM registers, into the hardware register that instantiates the specified 64-bit half of the one of the XMM registers the contents of the hardware registers that instantiate the EDX:EAX registers.

35. The method of claim 29 ,

wherein the microprocessor also includes hardware registers that instantiate the Advanced Vector Extensions (AVX) YMM registers;

wherein the microprocessor associates with each 64-bit quarter of the YMM registers a respective unique MSR address;

the method further comprising:

writing, by the microprocessor in response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of a 64-bit quarter of one of the YMM registers, into the hardware register that instantiates the specified 64-bit quarter of the one of the YMM registers the contents of the hardware registers that instantiate the EDX:EAX registers.

36. The method of claim 29 , wherein the WRMSR instruction is included in a program running on the microprocessor in an Intel 64 Architecture non-64-bit operating mode, wherein the WRMSR instruction writes debug data to the hardware register that instantiates the specified one of the R8-R15 GPRs for subsequent use in debugging the program.

Assignments (1)

Continuity (15)