IP Library › Granted Patent US 9,336,864
Granted Patent B2
US 9,336,864 · App. 14/473,974 · Granted May 10, 2016

Silicon germanium read port for a static random access memory register file

Inventors: Niladri Mojumder (San Diego, CA); Stanley Seungchul Song (San Diego, CA); Zhongze Wang (San Diego, CA); Choh Fei Yeap (San Diego, CA)
Assignee: QUALCOMM Incorporated
G11C11/419G11C11/405G11C11/409
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Quick Facts
Patent No.
US 9,336,864
App. No.
14/473,974
Granted
May 10, 2016
Kind
B2
Abstract

A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

Claims (55)

1. A static random access memory (SRAM) circuit comprising:

a write port; and

a read port coupled to the write port, the read port comprising:

a first p-type metal oxide semiconductor (PMOS) transistor having a first silicon germanium (SiGe) channel; and

a second PMOS transistor having a second SiGe channel, wherein the second PMOS transistor is coupled between the first PMOS transistor and a ground voltage,

wherein the first PMOS transistor and the second PMOS transistor are configured to discharge a read bit line.

2. The SRAM circuit of claim 1 , wherein the write port and the read port are included in an 8-transistor bit cell.

3. The SRAM circuit of claim 1 , wherein a source of the first PMOS transistor is coupled to the read bit line, and wherein a gate of the first PMOS transistor is coupled to a read word line.

4. The SRAM circuit of claim 1 , wherein a source of the second PMOS transistor is coupled to a drain of the first PMOS transistor, and wherein a drain of the second PMOS transistor is coupled to ground.

5. The SRAM circuit of claim 1 , further comprising a second read port coupled to the write port, the second read port comprising:

a second read bit line;

a third PMOS transistor having a third SiGe channel; and

a fourth PMOS transistor having a fourth SiGe channel, wherein the fourth PMOS transistor is coupled to the third PMOS transistor.

6. The SRAM circuit of claim 5 , wherein the write port and the read port are included in a 10-transistor bit cell.

7. The SRAM circuit of claim 5 , wherein the third PMOS transistor and the fourth PMOS transistor are configured to discharge the second read bit line.

8. The SRAM circuit of claim 7 , wherein a source of the third PMOS transistor is coupled to the second read bit line, and wherein a gate of the third PMOS transistor is coupled to a second read word line.

9. The SRAM circuit of claim 7 , wherein a source of the fourth PMOS transistor is coupled to a drain of the third PMOS transistor, and wherein a drain of the fourth PMOS transistor is coupled to ground.

10. The SRAM circuit of claim 1 , wherein the write port comprises a latch, the latch comprising:

a first inverter having an input coupled to a gate of the second PMOS transistor; and

a second inverter having an output coupled to the gate of the second PMOS transistor.

11. The SRAM circuit of claim 10 , wherein the first inverter comprises:

a first n-type metal oxide semiconductor (NMOS) transistor, wherein a gate of the first NMOS transistor is coupled to the gate of the second PMOS transistor; and

a fifth PMOS transistor having a fifth SiGe channel, wherein a gate of the fifth PMOS transistor is coupled to the gate of the second PMOS transistor.

12. The SRAM circuit of claim 11 , wherein the second inverter comprises:

a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to the gate of the second PMOS transistor; and

a sixth PMOS transistor having a sixth SiGe channel, wherein a drain of the sixth PMOS transistor is coupled to the gate of the second PMOS transistor;

wherein a gate of the second NMOS transistor is coupled to a gate of the sixth PMOS transistor.

13. The SRAM circuit of claim 12 , wherein a source of the first NMOS transistor is coupled to a source of the second NMOS transistor, and wherein a source of the fifth PMOS transistor is coupled to a source of the sixth PMOS transistor.

14. A method comprising:

storing a data value into a latch; and

sensing the data value at a read port of a static random access memory (SRAM) circuit, the read port including a first p-type metal oxide semiconductor (PMOS) transistor having a first silicon germanium (SiGe) channel and a second PMOS transistor, wherein sensing the data value includes:

pre-charging a read bit line coupled to a source of the first PMOS transistor, the read bit line pre-charged to a logic high voltage level; and

biasing a gate of the first PMOS transistor with a logic low voltage level.

15. The method of claim 14 , wherein the second PMOS transistor has a second SiGe channel.

16. The method of claim 14 , wherein the read bit line discharges when the data value corresponds to the logic low voltage level.

17. The method of claim 14 , wherein the read bit line remains charged when the data value corresponds to a logic high voltage level.

18. The method of claim 14 , wherein the SRAM circuit is an 8-transistor bit cell.

19. The method of claim 14 , wherein the SRAM circuit is a 10-transistor bit cell.

20. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform operations comprising:

storing a data value into a latch; and

sensing the data value at a read port of a static random access memory (SRAM) circuit, the read port including a first p-type metal oxide semiconductor (PMOS) transistor having a first silicon germanium (SiGe) channel and a second PMOS transistor, wherein sensing the data value includes:

pre-charging a read bit line coupled to a source of the first PMOS transistor, the read bit line pre-charged to a logic high voltage level; and

biasing a gate of the first PMOS transistor with a logic low voltage level.

21. The non-transitory computer-readable medium of claim 20 , wherein the second PMOS transistor has a second SiGe channel.

22. The non-transitory computer-readable medium of claim 20 , wherein the SRAM circuit is an 8-transistor bit cell.

23. The non-transitory computer-readable medium of claim 20 , wherein the SRAM circuit is a 10-transistor bit cell.

24. A static random access memory (SRAM) circuit comprising:

means for storing data; and

means for sensing data coupled to the means for storing data, the means for sensing data comprising:

a first p-type metal oxide semiconductor (PMOS) transistor having a first silicon germanium (SiGe) channel; and

a second PMOS transistor coupled to the first PMOS transistor,

wherein the first PMOS transistor and the second PMOS transistor are configured to discharge a read bit line.

25. The SRAM circuit of claim 24 , wherein the second PMOS transistor has a second SiGe channel.

26. The SRAM circuit of claim 24 , wherein the means for storing data and the means for sensing data are included in an 8-transistor bit cell.

27. The SRAM circuit of claim 24 , wherein the means for storing data and the means for sensing data are included in a 10-transistor bit cell.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2014
From: MOJUMDER, NILADRI; SONG, STANLEY SEUNGCHUL; WANG, ZHONGZE; YEAP, CHOH FEI
To: QUALCOMM INCORPORATED
Reel/Frame 033980/0175 →
Continuity (1)
Related Publication 20160064068A1 · Mar 3, 2016