IP Library › Granted Patent US 9,336,882

Granted Patent B2

US 9,336,882 · App. 14/281,433 · Granted May 10, 2016

Semiconductor storage device and driving method thereof

Inventors: Akira Katayama (Yamato, JP); Katsuhiko Hoya (Yokohama, JP); Keiichi Ryu (Kamakura, JP); Yasuharu Takagi (Chuo-ku, JP)

Assignee: KABUSHIKI KAISHA TOSHIBA

G11C14/0036 G11C5/147 G11C11/16

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Quick Facts

Patent No.: US 9,336,882
App. No.: 14/281,433
Granted: May 10, 2016
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A memory includes a cell array including nonvolatile memory cells. A power generator generates a power supply voltage for driving the cell array. A receiver receives a command and an address. A controller controls an active state of the cell array, the power generator, and the receiver. In an activation mode, the cell array, the power generator, and the receiver are turned into the active states. In a first power saving mode, the cell array, the power generator, and the receiver are turned into inactive states. In a second power saving mode, the cell array and the power generator are turned into the active states, and the receiver is turned into the inactive state. In a third power saving mode, at least a part of the power generator is turned into the active state, and the cell array and the receiver are turned into the inactive states.

Claims (57)

1. A semiconductor storage device comprising:

a memory cell array comprising a plurality of nonvolatile memory cells;

a power generator configured to generate a power supply voltage for driving the memory cell array;

a first receiver configured to receive a command and an address for controlling the memory cell array; and

a controller configured to control each of the memory cell array, the power generator, and the first receiver according to the command and the address, wherein

the device has an activation mode of turning the memory cell array, the power generator, and the first receiver into the active states; a first power saving mode of turning the memory cell array, the power generator, and the first receiver into inactive states; a second power saving mode of turning the memory cell array and the power generator into the active states and turning the first receiver into the inactive state; and a third power saving mode of turning at least a part of the power generator into the active state and turning the memory cell array and the first receiver into the inactive states.

2. The device of claim 1 , wherein when the first receiver receives a refresh command indicating a refresh operation for retaining data stored in a volatile memory, the device transitions to the third power saving mode.

3. The device of claim 1 , further comprising a second receiver configured to receive a clock enable signal for enabling the device to receive a clock signal, wherein

the second receiver is kept in an active state in the first to third power saving modes, and

the device returns from any one of the first to third power saving modes to the activation mode when the second receiver receives the clock enable signal.

4. The device of claim 2 , further comprising a second receiver configured to receive a clock enable signal for enabling the device to receive a clock signal, wherein

the second receiver is kept in an active state in the first to third power saving modes, and

the device returns from any one of the first to third power saving modes to the activation mode when the second receiver receives the clock enable signal.

5. The device of claim 1 , wherein

the power generator comprises at least a constant-voltage generator configured to generate a first voltage and a reference-voltage generator configured to generate a second voltage used to carry a current to the memory cells based on the first voltage generated by the constant-voltage generator, the first voltage being substantially constant, and

in the third power saving mode, at least one of the constant-voltage generator and the reference-voltage generator is turned into an inactive state.

6. The device of claim 2 , wherein

in the third power saving mode, at least one of the constant-voltage generator and the reference-voltage generator is turned into an inactive state.

7. The device of claim 3 , wherein

in the third power saving mode, at least one of the constant-voltage generator and the reference-voltage generator is turned into an inactive state.

8. The device of claim 1 , wherein

the power generator comprises: a constant-voltage generator configured to generate a first voltage which is substantially constant; a reference-voltage generator configured to generate a second voltage used to carry a current to the memory cells based on the first voltage generated by the constant-voltage generator; and a first booster configured to boost an external voltage toward a positive side or a second booster configured to boost the external voltage toward a negative side, and

in the third power saving mode, any part of the constant-voltage generator, the reference-voltage generator, or the first booster is turned into an inactive state, or any part of the constant-voltage generator, the reference-voltage generator, or the second booster is turned into the inactive state.

9. The device of claim 2 , wherein

10. The device of claim 3 , wherein

11. The device of claim 8 , wherein, in the third power saving mode, all of the constant-voltage generator, the reference-voltage generator, and the first booster are turned into the inactive states, or all of the constant-voltage generator, the reference-voltage generator, and the second booster are turned into the inactive states.

12. A method of driving a semiconductor storage device, the semiconductor storage device comprising: a memory cell array comprising a plurality of nonvolatile memory cells; a power generator configured to generate a power supply voltage; and a first receiver configured to receive a plurality of commands and a plurality of addresses for controlling the memory cell array,

the semiconductor storage device comprising:

an activation mode of turning the memory cell array, the power generator, and the first receiver into activated modes;

a first power saving mode of turning the memory cell array, the power generator, and the first receiver into inactive states;

a second power saving mode of turning the memory cell array and the power generator into the active states and turning the first receiver into the inactive state; and

a third power saving mode of turning at least a part of the power generator into the active state and turning the memory cell array and the first receiver into the inactive states,

the method comprising:

transitioning states of the semiconductor storage device between the activation mode and any one of the first to third power saving modes according to the plurality of commands.

13. The method of claim 12 , wherein, when the first receiver receives a refresh command indicating a refresh operation for retaining data stored in a volatile memory, the semiconductor storage device transitions to the third power saving mode.

14. The method of claim 12 , wherein

the semiconductor storage device further comprises a second receiver configured to receive a clock enable signal for enabling the semiconductor storage device to receive a clock signal, and

the second receiver is kept in an active state in the first to third power saving modes, and the semiconductor storage device returns from any one of the first to third power saving modes to the activation mode when the second receiver receives the clock enable signal.

15. The method of claim 13 , wherein

the semiconductor storage device further comprises a second receiver configured to receive a clock enable signal for enabling the semiconductor storage device to receive a clock signal, and

16. The method of claim 12 , wherein

the power generator comprises: a first booster configured to boost an external voltage toward a positive side; a second booster configured to boost the external voltage toward a negative side; a constant-voltage generator configured to generate a first voltage which is substantially constant; and a reference-voltage generator configured to generate a second voltage used to carry a current to the memory cells based on the first voltage generated by the constant-voltage generator, and

in the third power saving mode, at least one of the first booster, the second booster, and the constant-voltage generator is turned into an inactive state.

17. The method of claim 13 , wherein

in the third power saving mode, at least one of the first booster, the second booster, and the constant-voltage generator is turned into an inactive state.

18. The method of claim 14 , wherein

in the third power saving mode, at least one of the first booster, the second booster, and the constant-voltage generator is turned into an inactive state.

19. The method of claim 16 , wherein in the third power saving mode, all of the first booster unit, the second booster unit, and the constant-voltage generator are turned into the inactive states.

Assignments (5)

CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021

From: K.K. PANGEA

To: TOSHIBA MEMORY CORPORATION

Reel/Frame 055669/0401 →

MERGER Recorded Jan 22, 2021

From: TOSHIBA MEMORY CORPORATION

To: K.K. PANGEA

Reel/Frame 055659/0471 →

CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021

From: TOSHIBA MEMORY CORPORATION

To: KIOXIA CORPORATION