IP Library › Granted Patent US 9,337,159
Granted Patent B2
US 9,337,159 · App. 14/106,092 · Granted May 10, 2016

Semiconductor package with integrated microwave component

Inventors: Ernst Seler (Munich, DE); Maciej Wojnowski (Munich, DE); Walter Hartner (Bad Abbach, DE); Josef Boeck (Putzbrunn, DE)
Assignee: Infineon Technologies AG
H01L23/66H01L24/19H01L24/96H01L21/561H01L21/568H01L23/3128H01L2924/12042H01L2924/19105
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Quick Facts
Patent No.
US 9,337,159
App. No.
14/106,092
Granted
May 10, 2016
Kind
B2
Abstract

A semiconductor device package includes an encapsulant and a semiconductor chip. The semiconductor chip is at least partly embedded in the encapsulant. A microwave component including at least one electrically conducting wall structure is integrated in the encapsulant. Further, the semiconductor device package includes an electrical interconnect configured to electrically couple the microwave component to the semiconductor chip.

Claims (25)

1. A semiconductor device package, comprising:

an encapsulant;

a semiconductor chip at least partly embedded in the encapsulant;

a microwave component comprising at least one electrically conducting wall structure integrated in the encapsulant; and

an electrical interconnect configured to electrically couple the microwave component to the semiconductor chip.

2. The semiconductor device package of claim 1 , wherein the at least one electrically conducting wall structure comprises a row of conducting vias formed in the encapsulant or one or more conducting slots formed in the encapsulant.

3. The semiconductor device package of claim 1 , further comprising:

an insert embedded in the encapsulant, wherein the at least one electrically conducting wall structure comprises a row of conducting vias formed in the insert or one or more conducting slots formed in the insert or a metallization on a wall of the insert.

4. The semiconductor device package of claim 1 , wherein the electrical interconnect comprises one of a microstrip line and a coplanar line.

5. The semiconductor device package of claim 1 , further comprising:

an electrical redistribution layer arranged over a first main surface of the encapsulant, wherein the electrical redistribution layer comprises the electrical interconnect.

6. The semiconductor device package of claim 1 , wherein the microwave component comprises a rectangular waveguide having a first metal plate, a second metal plate arranged parallel to the first metal plate and the at least one electrically conducting wall structure connecting to the first metal plate and to the second metal plate.

7. The semiconductor device package of claim 6 , further comprising:

an electrical redistribution layer arranged over a first main surface of the encapsulant, wherein the electrical redistribution layer comprises the first metal plate of the rectangular waveguide.

8. The semiconductor device package of claim 6 , further comprising:

an electrically conducting layer disposed over a second main surface of the encapsulant, wherein the electrically conducting layer comprises the second metal plate of the rectangular waveguide.

9. The semiconductor device package of claim 6 , wherein the rectangular waveguide is selected from the group consisting of a filter, an antenna, a resonator, a filter array, a resonator array, an antenna array, a power combiner, and a power divider.

10. The semiconductor device package of claim 1 , wherein the microwave component is an electromagnetic shielding.

11. The semiconductor device package of claim 1 , wherein the encapsulant is one of a molding material or a laminate material.

12. A semiconductor device package, comprising:

an encapsulant;

a semiconductor chip at least partly embedded in the encapsulant; and

a rectangular waveguide comprising at least one electrically conducting wall structure integrated in the encapsulant,

wherein the rectangular waveguide comprises a first metal plate and a second metal plate and the at least one electrically conducting wall structure is connected to the first metal plate and to the second metal plate,

wherein at least one of the first and second metal plates is structured from a metallization layer arranged over a main surface of the encapsulant.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2013
From: SELER, ERNST; WOJNOWSKI, MACIEJ; HARTNER, WALTER; BOECK, JOSEF
To: INFINEON TECHNOLOGIES AG
Reel/Frame 031781/0732 →
Continuity (1)
Related Publication 20150171033A1 · Jun 18, 2015