Integrated circuit with configurable on-die termination
Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
1. A communication system comprising:
a first integrated circuit (IC) having:
a transmitter to transmit a differential signal; and
first differential pads to convey the differential signal from the first IC;
a differential channel coupled to the first differential pads to communicate the differential signal; and
a second IC having:
second differential pads coupled to the differential channel to receive the differential signal, the second differential pads including a first pad and a second pad; and
on-die termination circuitry that includes:
a common node;
a first termination leg extending between the common node and the first pad, the first termination leg including a first termination impedance;
a second termination leg extending between the common node and the second pad, the second termination leg including a second termination impedance; and
a third termination leg extending between the common node and a reference-voltage node, the third termination leg including a switch to selectively couple the common node to the reference-voltage node.
2. The system of claim 1 , the second IC including a receiver having differential input terminals each coupled to a respective one of the second differential pads.
3. The system of claim 1 , wherein at least one of the first termination impedance and the second termination impedance is adjustable.
4. The system of claim 1 , wherein the first termination leg includes a second switch connected in series with the first termination impedance and the second termination leg includes a third switch connected in series with the second termination impedance.
5. The system of claim 1 , further comprising a memory coupled to the switch to deliver a select signal to the switch.
6. The system of claim 5 , wherein the switch includes a transistor having a control terminal, and wherein the memory includes an output connected to the control terminal to deliver the select signal.
7. The system of claim 1 , wherein the third termination leg includes a capacitor.
8. The system of claim 7 , wherein the capacitor includes a control terminal to control a programmable capacitance, the second IC further including a memory having an output connected to the control terminal.
9. The system of claim 7 , wherein the capacitor is connected in series with the switch.
10. The system of claim 1 , the third termination leg further comprising an adjustable termination.
11. The system of claim 10 , wherein the adjustable termination comprises a third termination impedance.
12. The system of claim 11 , wherein the third termination impedance is connected in series with the switch.
13. The system of claim 1 , wherein the reference-voltage node is connected to ground.
14. An integrated-circuit (IC) comprising:
differential pads to receive a differential signal, the differential pads including a first pad and a second pad; and
on-die termination circuitry that includes:
a common node;
a first termination impedance between the common node and the first pad;
a second termination impedance between the common node and the second pad; and
circuitry to selectively couple the common node to a reference-voltage node, the circuitry including a capacitor between the common node and the reference-voltage node.
15. The IC of claim 14 , wherein at least one of the first termination impedance and the second termination impedance is an adjustable impedance.
16. The IC of claim 14 , further comprising a second switch between the common node and the first pad in series with the first termination impedance.
17. The IC of claim 16 , further comprising a third switch between the common node and the second pad in series with the second termination impedance.
18. The IC of claim 14 , wherein the capacitor is adjustable.
19. The IC of claim 14 , further comprising a resistor between the common node and the reference-voltage node in series with the capacitor.
20. A computer-readable medium having stored thereon a non-transitory data structure defining an integrated circuit, the data structure comprising:
first data representing first and second input pads to couple to an external signal channel;
second data defining differential pads to receive a differential signal, the differential pads including a first pad and a second pad; and
third data defining on-die termination circuitry that includes:
a common node;
a first termination impedance between the common node and the first pad;
a second termination impedance between the common node and the second pad; and
a switch to selectively couple the common node to a reference-voltage node.
21. The IC of claim 14 , wherein the circuitry to selectively couple the common node to a reference-voltage node includes a resistor.
22. The IC of claim 14 , the circuitry to selectively couple the common node to a reference-voltage node including a filter circuit.
23. The IC of claim 14 , wherein the circuitry performs a noise reducing function.