Semiconductor devices having conductive pads and methods of fabricating the same
A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.
1. A semiconductor device, comprising:
gate electrodes that are stacked in a vertical direction on a substrate;
vertical channel structures that penetrate the gate electrodes to electrically connect to the substrate;
conductive pads horizontally extending from the respective gate electrodes, wherein the conductive pads include a ground selection pad and a plurality of cell pads stacked above the ground selection pad; and
contact plugs including a ground selection plug electrically connected to the ground selection pad and a plurality of cell plugs electrically connected to respective ones of the cell pads;
wherein each conductive pad includes an extension area and a contact area underneath respective ones of the contact plugs,
wherein the contact areas of the cell pads are thicker than the extension areas of the cell pads in the vertical direction,
wherein the contact area of the ground selection pad has a same thickness as the extension area of the ground selection pad,
wherein each contact area of the cell pads includes a base part and a protrusion part that protrudes vertically from the base part, and
wherein an outer side surface of the base part horizontally protrudes more than an outer side surface of the protrusion part.
2. A semiconductor device, comprising:
gate electrodes that are stacked in a vertical direction on a substrate;
vertical channel structures that penetrate the gate electrodes to electrically connect to the substrate;
conductive pads horizontally extending from the respective gate electrodes, wherein the conductive pads include a ground selection pad and a plurality of cell pads stacked above the ground selection pad; and
contact plugs including a ground selection plug electrically connected to the ground selection pad and a plurality of cell plugs electrically connected to respective ones of the cell pads;
wherein each cell pad includes an extension area and a contact area underneath respective ones of the cell plugs,
wherein the contact areas of the cell pads are thicker than the extension areas of the cell pads in the vertical direction, and
wherein a portion of the extension area of one of the cell pads that is adjacent the contact area includes a recess.
3. The semiconductor device of claim 1 , wherein the extension area of one of the cell pads has substantially the same thickness as the gate electrode from which one of the conductive pads horizontally extends, and wherein each outer side surface of the base part of the cell pads is reverse tapered from a top of the protrusion part towards the substrate.
4. The semiconductor device of claim 1 , further comprising interlayer insulating layers disposed under each of the cell pads,
wherein each outer side surface of the base part of the cell pads is vertically aligned with an outer side surface of the interlayer insulating layer thereunder.
5. The semiconductor device of claim 1 , wherein an outer side surface of the protrusion part of the cell pads is vertically aligned with an outer side surface of the base part of the cell pads.
6. The semiconductor device of claim 1 , wherein the outer side surface of the base part of the conductive pads is reverse tapered from a top of the protrusion part towards the substrate, and
the outer side surface of the protrusion part of the cell pads and the outer side surface of the base part of the cell pads are smoothly continuous.
7. The semiconductor device of claim 1 , wherein the gate electrodes include ground selection gate electrodes, string selection gate electrodes, and cell gate electrodes stacked between the ground selection gate electrodes and the string selection gate electrodes, and
the conductive pads further include string selection pads above the cell pads.
8. The semiconductor device of claim 1 , wherein each vertical channel structure includes a vertical channel, a tunnel insulating layer, a charge storage layer, a blocking insulating layer, and a filling insulating layer.
9. The semiconductor device of claim 7 , wherein the contact plugs comprise string selection plugs that are electrically connected to the respective string selection pads, ground selection plugs that are electrically connected to the respective ground selection pads, and cell plugs that are electrically connected to the respective cell pads, and
wherein a first subset of the cell plugs are collinear with at least one of the ground selection plugs while the combination of the first subset of the cell plugs and the at least one of the ground selection plugs are not collinear with any of the string selection plugs.
10. The semiconductor device of claim 1 , wherein interfaces between upper surfaces and outer side surfaces of the thickened portions of the conductive pads are rounded.