PVT tolerant differential circuit

1. An automatically calibrated differential amplifier comprising:

an input stage differential amplifier configured to receive an input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and

a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations and to have a replica stage bias current, the replica stage differential amplifier comprising a feedback circuit configured to receive an output of the replica stage differential amplifier and to adjust the replica stage bias current according to the output of the replica stage differential amplifier,

wherein the input stage differential amplifier comprises a plurality of differential amplifier pairs that are coupled to each other at their inputs to receive the input differential signal.

2. The automatically calibrated differential amplifier of claim 1 ,

wherein the replica stage differential amplifier is configured to:

receive a reference differential signal;

differentially amplify the reference differential signal to provide a replica stage output differential signal; and

provide a reference current based on the replica stage output differential signal, and

wherein the replica stage bias current and the input stage bias current are based on the reference current.

3. An automatically calibrated differential amplifier comprising:

an input stage differential amplifier configured to receive an input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current, the input stage differential amplifier comprising a plurality of differential amplifier pairs that are coupled to each other at their inputs to receive the input differential signal; and

a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations,

wherein the replica stage differential amplifier is configured to:

receive a reference differential signal;

differentially amplify the reference differential signal to provide a replica stage output differential signal; and

provide a reference current based on the replica stage output differential signal,

wherein a replica stage bias current and the input stage bias current are based on the reference current,

wherein the replica stage differential amplifier comprises:

a first amplifier leg;

a second amplifier leg; and

a feedback circuit coupled to the first amplifier leg and the second amplifier leg, and configured to output the reference current,

wherein the first amplifier leg and the second amplifier leg, together, are configured to differentially amplify the reference differential signal to provide the replica stage output differential signal,

wherein the feedback circuit receives the replica stage output differential signal and outputs the reference current according to the replica stage output differential signal, and

wherein a sum of a first amplifier leg current of the first amplifier leg and a second amplifier leg current of the second amplifier leg equals the replica stage bias current.

4. The automatically calibrated differential amplifier of claim 3 ,

wherein the feedback circuit comprises a comparator and a current generator, and

wherein the comparator is configured to receive the replica stage output differential signal and to control the current generator to increment or decrement the reference current according to the replica stage output differential signal.

5. The automatically calibrated differential amplifier of claim 3 ,

wherein the feedback circuit comprises an amplifier and a transistor, the transistor being configured to output the reference current, and

wherein the amplifier is configured to receive the replica stage output differential signal and to control a gate voltage of the transistor according to the replica stage output differential signal to adjust the reference current.

6. The automatically calibrated differential amplifier of claim 2 ,

wherein the replica stage differential amplifier further comprises:

a first resistor having a first terminal coupled to a voltage source, and a second terminal;

a second resistor having a first terminal coupled to the voltage source, and a second terminal;

a first current sink configured to sink a first current;

a second current sink configured to sink a second current;

a first transistor having a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the first current sink, and a gate terminal configured to receive a first reference signal of the reference differential signal;

a second transistor having a first terminal coupled to the second terminal of the second resistor, a second terminal coupled to the first current sink, and a gate terminal configured to receive a second reference signal of the reference differential signal;

a third transistor having a first terminal coupled to the second terminal of the second resistor, a second terminal coupled to the second current sink, and a gate terminal configured to receive the second reference signal of the reference differential signal;

a fourth transistor having a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the second current sink, and a gate terminal configured to receive the first reference signal of the reference differential signal; and

the feedback circuit configured to receive the replica stage output differential signal from the first terminal of the first transistor and the first terminal of the second transistor, and to output the reference current,

wherein the first current and the second current are based on the reference current, and

wherein a sum of the first current and the second current equals the replica stage bias current.

7. The automatically calibrated differential amplifier of claim 2 , further comprising a current mirror coupled to the input stage differential amplifier and the replica stage differential amplifier,

wherein the current mirror copies the reference current to control the input stage bias current.

8. The automatically calibrated differential amplifier of claim 1 ,

wherein the input stage differential amplifier comprises a first amplifier leg comprising a first transistor and a second amplifier leg comprising a second transistor, and is configured to be at an input stage of a comparator,

wherein the first amplifier leg and the second amplifier leg, together, are configured to differentially amplify the differential input signal,

wherein the input stage differential amplifier is configured to have an input offset voltage, and

wherein the input offset voltage corresponds to a difference between a bulk potential of the first transistor and a bulk potential of the second transistor.

9. A multilevel signal receiver comprising:

an input terminal configured to receive a multilevel differential signal;

a data slicer coupled to the input terminal and configured to determine voltage levels of the multilevel differential signal, the data slicer comprising a plurality of input stage comparators and a replica stage comparator; and

a decoder coupled to an output of the data slicer and configured to decode bits of the multilevel differential signal,

wherein each of the input stage comparators comprises an input stage differential amplifier, the input stage differential amplifier comprising:

a first amplifier leg; and

a second amplifier leg,

wherein the first amplifier leg and the second amplifier leg, together, are configured to differentially amplify the multilevel differential signal to provide a threshold determination signal,

wherein the input stage differential amplifier is configured to have an input offset voltage and an input stage bias current, and

wherein each of the input stage comparators is configured to have a threshold level different from the threshold level of other ones of the input comparators,

wherein each of the input stage comparators is configured to output its threshold determination signal to the decoder to indicate whether or not the multilevel signal is greater than its threshold level,

wherein, for each of the input stage comparators, the threshold level corresponds to the input offset voltage of the input stage differential amplifier,

wherein the replica stage comparator comprises a replica stage differential amplifier, the replica stage differential amplifier comprising:

a first amplifier leg;

a second amplifier leg; and

a feedback circuit configured to automatically adjust a replica stage bias current according to a replica stage differential output signal, and

wherein, for each of the input stage comparators, the input stage bias current of the input stage differential amplifier is based on the replica stage bias current.

10. The multilevel signal receiver of claim 9 :

wherein the replica stage differential amplifier is configured to:

receive a reference differential signal;

differentially amplify the reference differential signal to provide the replica stage output differential signal; and

provide a reference current based on the replica stage output differential signal, and

wherein the replica stage bias current and the input stage bias current are based on the reference current.

11. The multilevel signal receiver of claim 10 ,

wherein the feedback circuit is coupled to the first amplifier leg and the second amplifier leg of the replica stage differential amplifier, and configured to output the reference current,

wherein the first amplifier leg and the second amplifier leg of the replica stage differential amplifier, together, are configured to differentially amplify the reference differential signal to provide the replica stage output differential signal,

wherein the feedback circuit receives the replica stage output differential signal and outputs the reference current according to the replica stage output differential signal, and

wherein a sum of a first amplifier leg current of the first amplifier leg and a second amplifier leg current of the second amplifier leg equals the replica stage bias current.

12. The multilevel signal receiver of claim 11 ,

wherein the feedback circuit comprises a comparator and a current generator, and

wherein the comparator is configured to receive the replica stage output differential signal and to control the current generator to increment or decrement the reference current according to the replica stage output differential signal.

13. The multilevel signal receiver of claim 11 ,

wherein the feedback circuit comprises an amplifier and a transistor, the transistor being configured to output the reference current, and

wherein the amplifier is configured to receive the replica stage output differential signal and to control a gate voltage of the transistor according to the replica stage output differential signal to adjust the reference current.

14. The multilevel signal receiver of claim 11 , further comprising a current mirror coupled to the input stage differential amplifier of each of the input stage comparators and the replica stage differential amplifier,

wherein the current mirror copies the reference current to control the input stage bias current of the input stage differential amplifier of each of the input stage comparators.

15. The multilevel signal receiver of claim 9 ,

wherein the replica stage differential amplifier further comprises:

a first resistor having a first terminal coupled to a voltage source, and a second terminal;

a second resistor having a first terminal coupled to the voltage source, and a second terminal;

a first current sink configured to sink a first current;

a second current sink configured to sink a second current;

a first transistor having a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the first current sink, and a gate terminal configured to receive a first reference signal of a reference differential signal;

a second transistor having a first terminal coupled to the second terminal of the second resistor, a second terminal coupled to the first current sink, and a gate terminal configured to receive a second reference signal of the reference differential signal;

a third transistor having a first terminal coupled to the second terminal of the second resistor, a second terminal coupled to the second current sink, and a gate terminal configured to receive the second reference signal of the reference differential signal;

a fourth transistor having a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the second current sink, and a gate terminal configured to receive the first reference signal of the reference differential signal; and

a feedback circuit configured to receive the replica stage output differential signal from the first terminal of the first transistor and the first terminal of the second transistor, and to output a reference current,

wherein the first current and the second current are based on the reference current, and

wherein a sum of the first current and the second current equals the replica stage bias current.

16. The multilevel signal receiver of claim 15 , wherein the input offset voltage of the input stage differential amplifier of at least one of the input stage comparators corresponds to a difference between a bulk potential of the first transistor and a bulk potential of the second transistor.