Memory centric computing
A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.
1. A method for processing data in a hybrid memory system, the method comprising:
providing a hybrid memory system comprising:
a processor; a hybrid memory buffer (HMB) module coupled to the processor, a plurality of a first memory modules coupled to the HMB module and a plurality of a second memory modules coupled to the HMB module, wherein the HMB comprises a Near-Memory-Processing (NMP) module, a memory storage controller (MSC) module coupled to the processor, and a Serializer/Deserializer (SerDes) interface coupled to the NMP module and the MSC module;
determining, by the processor, an address of a target data page from the plurality of second memory modules;
determining, by the processor, an index of a target buffer destination in an SRAM buffer provided in the NMP module;
initiating, by the processor, transfer of the target data page to the target buffer destination via writing to control and status registers provided in the MSC module; and
updating, by the processor, a data status related to the target data page and the target buffer destination in the control and status registers using the HMB module;
retrieving, by the HMB module, sixteen 4-byte data or eight 8-byte data from one or more data pages from the plurality of first or second memory modules;
combining, by the HMB module, the sixteen 4-byte data or eight 8-byte data into a single 64-byte data; and
determining, by the HMB module, an ECC (Error Correcting Code) parity for the single 64-byte data.
2. The method of claim 1 wherein the plurality of first memory modules comprises RAM (Random Access Memory) modules, DRAM (Dynamic RAM) modules, or SDRAM (Synchronous DRAM).
3. The method of claim 1 wherein the plurality of second memory modules comprises flash memory modules, NAND flash memory modules, vertical NAND flash memory modules, or NOR flash memory modules.
4. The method of claim 1 wherein the HMB is configured to monitor and manage wear leveling and garbage collection.
5. The method of claim 1 wherein the plurality first memory modules and the plurality of second memory modules are configured as a plurality of hybrid memory modules having each of the first memory modules associated with one of the second memory modules, and further comprising
initiating, by the processor, a memory check pointing process wherein each of the plurality of hybrid memory modules is configured to move data from the first memory module to the second memory module independently using the HMB module.
6. The method of claim 1 further comprising
configuring the HMB, by the processor, a set of ECC (Error Correcting Code) symbols associated with the data status;
initiating, by the processor, a status return request to the HMB module; and
returning, from the HMB module, a status return associated with the data status based on the set of ECC symbols.
7. The method of claim 1 wherein the HMB is configured to provide ECC (Error Correcting Code) parity generation via a hardware state machine or via programmable ECC-parity generation circuit provided in the hybrid memory system.
8. The method of claim 1 further comprising performing, by the HMB module, a page initialization process wherein a data page in the plurality of first or second memory modules is initialized to a predetermined data pattern using the NMP module.
9. A method for processing data in a hybrid memory system, the method comprising:
providing a hybrid memory system comprising:
a processor; a hybrid memory buffer (HMB) module coupled to the processor, a plurality of a first memory modules coupled to the HMB module and a plurality of a second memory modules coupled to the HMB module, wherein the HMB comprises a Near-Memory-Processing (NMP) module, a memory storage controller (MSC) module coupled to the processor, and a Serializer/Deserializer (SerDes) interface coupled to the NMP module and the MSC module;
determining, by the processor, an address of a target data page from the plurality of second memory modules;
determining, by the processor, an index of a target buffer destination in an SRAM buffer provided in the NMP module;
initiating, by the processor, transfer of the target data page to the target buffer destination via writing to control and status registers provided in the MSC module;
updating, by the processor, a data status related to the target data page and the target buffer destination in the control and status registers using the HMB module;
retrieving, by the HMB module, sixteen 4-byte data or eight 8-byte data from one or more data pages from the plurality of first or second memory modules;
combining, by the HMB module, the sixteen 4-byte data or eight 8-byte data into a single 64-byte data;
determining, by the HMB module, an ECC (Error Correcting Code) parity for the single 64-byte data;
retrieving, by the HMB module, a single 64-byte data from a data page from the plurality of first or second memory modules;
performing, by the HMB module, a scatter process wherein the single 64-byte data is split into data segments comprising sixteen 4-byte data or eight 8-byte data; and
determining, by the HMB module, an ECC (Error Correcting Code) parity for each of the data segments.
10. The method of claim 9 wherein the plurality of first memory modules comprises RAM (Random Access Memory) modules, DRAM (Dynamic RAM) modules, or SDRAM (Synchronous DRAM).
11. The method of claim 9 wherein the plurality of second memory modules comprises flash memory modules, NAND flash memory modules, vertical NAND flash memory modules, or NOR flash memory modules.
12. The method of claim 9 wherein the HMB is configured to monitor and manage wear leveling and garbage collection.
13. The method of claim 9 wherein the plurality first memory modules and the plurality of second memory modules are configured as a plurality of hybrid memory modules having each of the first memory modules associated with one of the second memory modules, and further comprising
initiating, by the processor, a memory check pointing process wherein each of the plurality of hybrid memory modules is configured to move data from the first memory module to the second memory module independently using the HMB module.
14. The method of claim 9 further comprising
configuring the HMB, by the processor, a set of ECC (Error Correcting Code) symbols associated with the data status;
initiating, by the processor, a status return request to the HMB module; and
returning, from the HMB module, a status return associated with the data status based on the set of ECC symbols.
15. The method of claim 9 wherein the HMB is configured to provide ECC (Error Correcting Code) parity generation via a hardware state machine or via programmable ECC-parity generation circuit provided in the hybrid memory system.
16. The method of claim 9 further comprising performing, by the HMB module, a page initialization process wherein a data page in the plurality of first or second memory modules is initialized to a predetermined data pattern using the NMP module.