Structure and method for FinFET device

1. A fin-like field-effect transistor (FinFET) device comprising:

a fin structure disposed over a substrate, the fin structure including:

a semiconductor oxide layer disposed over the substrate, wherein the semiconductor oxide layer has a top surface facing away from the substrate;

a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer, wherein the first semiconductor material layer has a top surface facing away from the substrate and an opposing bottom surface facing the substrate; and

a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer;

a gate dielectric layer disposed over the fin structure, wherein the gate dielectric layer physically contacts the top surface and the bottom surface of the first semiconductor layer and physically contacts the top surface of the semiconductor oxide layer; and

a gate electrode layer disposed over the gate dielectric layer, wherein the gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer.

2. The device of claim 1 , further comprising:

a source/drain (S/D) feature adjacent to the fin-like structure, including:

a second semiconductor material layer over the substrate, wherein the second semiconductor material layer has a different material than the first semiconductor material layer.

3. The device of claim 2 , wherein the S/D feature physically contacts the dielectric sidewall spacer.

4. The device of claim 2 , wherein the S/D feature physically contacts the first semiconductor material layer.

5. The device of claim 1 , wherein the gate electrode layer is isolated from the S/D feature by the dielectric sidewall spacer.

6. The device of claim 1 , wherein the gate electrode layer is isolated from the substrate by the semiconductor oxide layer member.

7. The device of claim 1 , wherein:

the semiconductor oxide layer includes silicon germanium oxide (SiGeO);

the first semiconductor material layer includes silicon (Si);

the dielectric sidewall spacer includes silicon nitride;

the gate dielectric layer includes high-k dielectric layer; and

the gate electrode layer includes metal gate layer.

8. The device of claim 1 , further comprising:

a plurality of isolation features over the substrate, wherein:

a multiple of the fin-like structures, wrapped by the gate dielectric layer and the gate electrode layer, disposed between two adjacent isolation features; and

the S/D feature disposed between two adjacent isolation features.

9. The device of claim 8 , wherein the multiple of the fin-like structures, between two adjacent isolation features, have a common gate electrode layer.

10. The device of claim 8 , wherein the S/D feature physically contacts to the respective first semiconductor material layer of each of the multiple fin-like structures.

11. A fin-like field-effect transistor (FinFET) device comprising:

a fin structure disposed over a substrate, the fin structure including:

semiconductor oxide layer disposed over the substrate, wherein the semiconductor oxide layer has a top surface facing away from the substrate;

a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer, wherein the first semiconductor material layer has a top surface facing away from the substrate and an opposing bottom surface facing the substrate; and

a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer;

a high-k/metal gate (HK/MG) disposed over the fin structure, wherein the HK/MG gate extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer; and

a source/drain (S/D) feature adjacent to the fin-like structure, wherein the S/D features physically contacts:

the dielectric sidewall spacer; and

the first semiconductor material layer;

a gate dielectric layer disposed over the fin structure, wherein the gate dielectric layer physically contacts the top surface and the bottom surface of the first semiconductor layer and physically contacts the top surface of the semiconductor oxide layer; and

a gate electrode layer disposed over the gate dielectric layer, wherein the gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer.

12. The device of claim 11 , wherein the HK/MG is isolated from the S/D feature by the dielectric sidewall spacer.

13. The device of claim 11 , wherein the HK/MG is isolated from the substrate by the semiconductor oxide layer.

14. The device of claim 11 , further comprising:

isolation features over the substrate;

an additional plurality of fin-like structures, each of the additional plurality of fin-like structures having a HK/MG disposed between two adjacent isolation features.

15. The device of claim 14 , wherein each of the FIK/MGs of the additional of the fin-like structures between two adjacent isolation features, have a common HK/MG.

16. The device of claim 15 , wherein a S/D feature of each of the additional plurality of fin-like structures physically contacts a semiconductor material layer of each of the additional plurality of fin-like structures.

17. A fin-like field-effect transistor (FinFET) device comprising:

a fin structure disposed over a substrate, the fin structure including:

a semiconductor oxide layer disposed over the substrate;

a first semiconductor material layer disposed over and spaced apart from the semiconductor oxide layer; and

a dielectric sidewall spacer disposed along a sidewall of the semiconductor oxide layer and extending to the first semiconductor material layer;

a gate dielectric layer disposed over and physically contacting a top surface and a bottom surface of the first semiconductor layer; and

a gate electrode layer disposed over the gate dielectric layer, wherein the gate electrode extends between the top surface of the semiconductor oxide layer and the bottom surface of the first semiconductor material layer.

18. The device of claim 17 , wherein the gate dielectric layer is disposed over and physically contacts a top surface of the semiconductor oxide layer.

19. The device of claim 17 , wherein an outer surface of the dielectric sidewall spacer is coplanar with an outer surface of the first semiconductor material layer.

20. The device of claim 17 , wherein the gate electrode layer is isolated from the substrate by the semiconductor oxide layer member.