Hybrid approach to write assist for memory array
A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
1. A hybrid write-assist memory system, comprising:
an array voltage supply;
a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply;
a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation, wherein the voltage reduction of the separable cell supply voltage is provided through a charge sharing connection with an upper metal capacitance and an upper metal coupling capacitance during an initial portion of the write operation; and
a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation.
2. The system as recited in claim 1 wherein the separable cell supply voltage is coupled to the array voltage supply before and after the write operation.
3. The system as recited in claim 1 wherein a first control signal initiates the voltage reduction of the separable cell supply voltage and a second control signal initiates the negative bit line voltage.
4. The system as recited in claim 1 wherein the upper metal capacitance and the upper metal coupling capacitance are fringing capacitances.
5. The system as recited in claim 1 wherein a shared charge on the upper metal coupling capacitance is further coupled to one of the bit lines through a bit line coupling connection to provide the negative bit line voltage during a remaining portion of the write operation.
6. The system as recited in claim 1 wherein a local compensation capacitor is provided in parallel with the upper metal coupling capacitance to maintain a constant array bit line capacitance ratio.
7. The system as recited in claim 1 wherein the upper metal capacitance and the upper metal coupling capacitance are provided by respective first and second upper metal structures having a plurality of metal wires that are constructed in parallel with array bit lines and array voltage supply lines.
8. The system as recited in claim 7 wherein the first and second upper metal structures are interleaved structures.
9. The system as recited in claim 7 wherein the first and second upper metal structures are a same height as array bit lines.
10. A method of operating a hybrid write-assist memory system, comprising:
providing an array supply voltage;
providing a static random access memory (SRAM) cell controlled by bit lines and a word line and that employs a separable cell supply voltage coupled to the array supply voltage;
generating a reduction of the separable cell supply voltage during a write operation, wherein the voltage reduction of the separable cell supply voltage is provided through a charge sharing with an upper metal capacitance and an upper metal coupling capacitance during an initial portion of the write operation; and
establishing a negative bit line voltage together with the reduction of the separable cell supply voltage during the write operation.
11. The method as recited in claim 10 wherein the separable cell supply voltage is equal to the array supply voltage before and after the write operation.
12. The method as recited in claim 10 wherein a first control signal initiates the voltage reduction of the separable cell supply voltage and a second control signal initiates the negative bit line voltage.
13. The method as recited in claim 10 wherein the upper metal capacitance and the upper metal coupling capacitance are fringing capacitances.
14. The method as recited in claim 10 wherein a shared charge on the upper metal coupling capacitance is further coupled to one of the bit lines to provide the negative bit line voltage during a remaining portion of the write operation.
15. The method as recited in claim 10 wherein a local compensation capacitor is provided in parallel with the upper metal coupling capacitance to maintain a constant array bit line capacitance ratio.
16. The method as recited in claim 10 wherein the upper metal capacitance and the upper metal coupling capacitance are provided by respective first and second upper metal structures having a plurality of metal wires that are constructed in parallel with array bit lines and array supply voltage lines.
17. The method as recited in claim 16 wherein the first and second upper metal structures are interleaved structures.
18. The method as recited in claim 16 wherein the first and second upper metal structures are a same height as array bit lines.