Memory device and memory system including the same
A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.
1. A memory device comprising:
a plurality of memory banks;
a row control signal input unit suitable for receiving a plurality of row control signals, wherein the row control signals include one or more row control signals and one or more first address signals;
a column control signal input unit suitable for receiving a plurality of column control signals, wherein the column control signals include one or more column control signals and one or more second address signals;
a row control unit suitable for selecting a first memory bank among the plurality of memory banks and a row in response to the row control signals, and controlling a row operation for the selected row; and
a column control unit suitable for selecting the first memory bank or another memory bank among the plurality of memory banks and a column in response to the column control signals, and controlling a column operation for the selected column,
wherein the row control signal input unit sequentially receives the row control signals through a plurality of row input pads, and the column control signal input unit sequentially receives the column control signals through a plurality of column input pads, and
wherein one or more row input pads among the plurality of row input pads receives the row control signals and the first address signals, and one or more column input pads among the plurality of column input pads receives the column control signals and the second address signals.
2. The memory device of claim 1 , wherein the number of the row input pads is less than the number of the row control signals, and
the number of the column input pads is less than the number of the column control signals.
3. The memory device of claim 1 , wherein the first address signals comprise one or more row bank address signals, and one or more row address signals, and
the second address signals comprise one or more column bank address signals, and one or more column addresses.
4. The memory device of claim 2 , wherein the row operation comprises an active operation, a precharge operation, a refresh operation, and a power down operation, and
the column operation comprises a read operation, a write operation, and a mode register setting operation.
5. The memory device of claim 1 , wherein the plurality of memory banks forms a plurality of bank groups each comprising one or more memory banks, and
the row control signals for one bank group among the bank groups and the column control signals for another bank group are inputted simultaneously.
6. A memory system comprising:
a memory device including a plurality of memory banks, suitable for sequentially receiving a plurality of row control signals through a plurality of row input pads, selecting a first memory bank among the plurality of memory banks and a row, and performing a row operation for the selected row, and suitable for sequentially receiving a plurality of column control signals through a plurality of column input pads, selecting the first memory bank or another memory bank among the plurality of memory banks and a column, and performing a column operation for the selected column; and
a memory controller suitable for transmitting the row control signals and the column control signals to the memory device, to control the memory device
wherein the row control signals include one or more row command signals and one or more first address signals, the column control signals include one or more column command signals and one or more second address signals, and
wherein one or more row input pads among the plurality of row input pads receives the row command signals and the first address signals, and one or more column input pads among the plurality of column input pads receives the column command signals and the second address signals.
7. The memory system of claim 6 , wherein the number of the row input pads is less than the number of the row control signals, and
the number of the column input pads is less than the number of the column control signals.
8. The memory system of claim 7 , further comprising:
a row channel coupled between the memory device and the memory controller, and suitable for transmitting the row control signals; and
a column channel coupled between the memory device and the memory controller, and suitable for transmitting the column control signals.
9. The memory system of claim 7 , wherein the first address signals comprise one or more row bank address signals and one or more row address signals, and
the second address signals comprise one or more column bank address signals and one or more column address signals.
10. The memory system of claim 7 , wherein the row operation comprises an active operation, a precharge operation, a refresh operation, and a power down operation, and
the column operation comprises a read operation, a write operation, and a mode register setting operation.
11. The memory system of claim 7 , wherein the plurality of memory banks forms a plurality of bank groups each comprising one or more memory banks, and
the memory controller transmits the row control signals for one bank group among the bank groups and the column control signals for another bank group to the memory device.