Parallel sample-and-hold circuit for a pipelined ADC
A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples.
1. A converter stage for a pipelined analog-to-digital converter (ADC), comprising:
an ADC configured to convert a first sample of an analog signal into a digital value, wherein the ADC comprises a first sampling switch configured to couple the analog signal to a first hold capacitor to store the first sample of the analog signal on the first hold capacitor;
a multiplying digital-to-analog converter (MDAC) configured to convert the digital value into an analog value and subtract the analog value from a second sample of the analog signal to provide a residue, wherein the MDAC comprises a second sampling switch configured to couple the analog signal to a second hold capacitor to store the second sample of the analog signal on the second hold capacitor;
a first compensation switch coupled between a first terminal of the first hold capacitor and a first terminal of the second hold capacitor; and
a second compensation switch coupled between a second terminal of the first hold capacitor and a second terminal of the second hold capacitor.
2. The converter stage of claim 1 , wherein the first compensation switch is configured to equalize a voltage of the first sample of the analog signal on the first hold capacitor with a voltage of the second sample of the analog signal on the second hold capacitor.
3. The converter stage of claim 1 , wherein the first compensation switch is configured to equalize a voltage on the first terminal of the first hold capacitor with a voltage on the first terminal of the second hold capacitor.
4. The converter stage of claim 1 , wherein the second compensation switch is configured to equalize a voltage on the second terminal of the first hold capacitor with a voltage on the second terminal of the second hold capacitor.
5. The converter stage of claim 1 , further comprising a controller configured to provide a first control signal to control the first and second sampling switches and a second control signal to control the first and second compensation switches.
6. The converter stage of claim 5 , wherein the controller is further configured to provide the first control signal and the second control signal such that the first and second compensation switches, are closed after the first and second sampling switches are opened.
7. The converter stage of claim 5 , wherein the controller is further configured to provide the second control signal with a delayed falling edge as compared to a falling edge of the first control signal.
8. The converter stage of claim 1 , wherein the MDAC is further configured to amplify the residue.
9. A converter stage for a pipelined analog-to-digital converter (ADC), comprising:
an ADC configured to convert a first sample of an analog signal into a digital value, wherein the ADC comprises a first sampling switch configured to couple the analog signal to a first hold capacitor to store the first sample of the analog signal on the first hold capacitor;
a multiplying digital-to-analog converter (MDAC) configured to convert the digital value into an analog value and subtract the analog value from a second sample of the analog signal to provide a residue, wherein the MDAC comprises a second sampling switch configured to couple the analog signal to a second hold capacitor to store the second sample of the analog signal on the second hold capacitor; and
a first compensation switch configured to equalize a voltage of the first sample of the analog signal on the first hold capacitor with a voltage of the second sample of the analog signal on the second hold capacitor.
10. The converter stage of claim 9 , wherein the first compensation switch is coupled between a first terminal of the first hold capacitor and a first terminal of the second hold capacitor.
11. The converter stage of claim 9 , further comprising a controller configured to provide a first control signal to control the first and second sampling switches and a second control signal to control the first compensation switch.
12. The converter stage of claim 11 , wherein the controller is further configured to provide the first control signal and the second control signal such that the first compensation switch is closed after the first and second sampling switches are opened.
13. The converter stage of claim 11 , wherein the controller is further configured to provide the second control signal with a delayed falling edge as compared to a falling edge of the first control signal.
14. A parallel sample-and-hold circuit, comprising:
a first sampling switch configured to couple an analog signal to a first hold capacitor to store a first sample of the analog signal on the first hold capacitor;
a second sampling switch configured to couple the analog signal to a second hold capacitor to store a second sample of the analog signal on the second hold capacitor; and
a first compensation switch coupled between a first terminal of the first hold capacitor and a first terminal of the second hold capacitor, wherein the first compensation switch is configured to equalize a voltage of the first sample of the analog signal on the first hold capacitor with a voltage of the second sample of the analog signal on the second hold capacitor.
15. The parallel sample-and-hold circuit of claim 14 , further comprising:
a second compensation switch coupled between a second terminal of the first hold capacitor and a second terminal of the second hold capacitor.
16. The parallel sample-and-hold circuit of claim 15 , wherein the first compensation switch is configured to equalize a voltage on the first terminal of the first hold capacitor with a voltage on the first terminal of the second hold capacitor.
17. The parallel sample-and-hold circuit of claim 15 , wherein the second compensation switch is configured to equalize a voltage on the second terminal of the first hold capacitor with a voltage on the second terminal of the second hold capacitor.
18. The parallel sample-and-hold circuit of claim 15 , further comprising a controller configured to provide a first control signal to control the first and second sampling switches and a second control signal to control the first and second compensation switches.
19. The parallel sample-and-hold circuit of claim 18 , wherein the controller is further configured to provide the first control signal and the second control signal such that the first and second compensation switches are closed after the first and second sampling switches are opened.
20. The parallel sample-and-hold circuit of claim 18 , wherein the controller is further configured to provide the second control signal with a delayed falling edge as compared to a corresponding falling edge of the first control signal.