Pixel design for flexible active matrix array

1. A flexible active matrix array, the array comprising:

a flexible substrate;

an array of pixels overlying the substrate, each pixel having a length (L) and a width (W), and comprising an active device and a light controlling device;

a plurality of parallel row lines overlying the substrate, each row line formed in a serpentine pattern with a plurality of partial-loops having a period (T 1 ), to supply a first signal to a corresponding plurality of pixels; and,

a plurality of parallel column lines overlying the substrate, orthogonal to the row lines, each column line formed in a serpentine pattern with a plurality of partial-loops having a period (T 2 ), to supply a second signal to a corresponding plurality of pixels; and,

wherein T 1 is greater than L, and wherein T 2 is greater than W.

2. The array of claim 1 wherein each pixel has a border;

wherein each row line partial-loop is formed along about 75% of a corresponding pixel border; and,

wherein each column line partial-loop is formed along about 75% of a corresponding pixel border.

3. The array of claim 2 wherein each row line partial-loop has an opening on a corresponding pixel border; and,

wherein each column line partial-loop has an opening on a corresponding pixel border, orthogonal to the row line partial-loop opening.

4. The array of claim 3 wherein the row line partial-loop openings of row-adjacent pixels are 180 degrees out of phase; and,

wherein the column line partial-loop openings of column-adjacent pixels are 180 degrees out of phase.

5. The array of claim 4 wherein the row line partial-loop openings of column-adjacent pixels are 180 degrees out of phase; and,

wherein the column line partial-loop openings of row-adjacent pixels are 180 degrees out of phase.

6. The array of claim 4 wherein the row line partial-loops have a 3-sided rectangular shape comprising a first side, a middle side, and a last side; and,

wherein a middle side of a row line partial-loop for a pixel in a (2n +1)th row and a (2m +2)th column, where n and m are integers greater than or equal to zero, is parallel to and adjacent a middle side of a row line for a pixel in a (2n +2)th row and the (2m +2)th column.

7. The array of claim 6 wherein the column line partial-loops have a 3-sided rectangular shape comprising a first side, a middle side, and a last side; and,

wherein a middle side of a column line partial-loop for a pixel in the (2n +1)th row and a (2m +1)th column, is parallel to and adjacent a middle side of a column line for a pixel in the (2n +1)th row and the (2m +2)th column.

8. The array of claim 7 wherein the row and column line partial-loops have a 3-sided rectangular shape with chamfered corners.

9. The array of claim 8 wherein the row and column line partial loops cross at their respective chamfered corners.

10. The array of claim 6 wherein a last side of a row line partial-loop for a first pixel is a first side of a row line partial-loop of a second pixel, adjacent to the first pixel in a row.

11. The array of claim 7 wherein a last side of a column line partial-loop for a first pixel is a first side of a column line partial-loop of a second pixel, adjacent to the first pixel in a column.

12. The array of claim 4 wherein row and column line partial-loops have a side length of X in a first axis; and,

wherein the substrate has a minimum radius of curvature of V=0.5X in the first axis.

13. The array of claim 2 wherein the row and column line partial-loops have a shape selected from a group consisting of a 3-sided rectangular and semicircular with an arc of 270 degrees.

14. The array of claim 1 wherein the row and column lines have a width in a range of 5 to 20 microns, and a thickness in a range of 1 to 2 microns.

15. The array of claim 1 wherein the active device comprises at least one thin-film transistor (TFT) and the light controlling device is selected from a group consisting of a light emitting device (LED), a transparent electrode connected to an underlying liquid crystal (LC) region, and a photodiode.

16. The array of claim 1 wherein the flexible substrate is selected from a group consisting of transparent, semi-transparent, and opaque.

17. The array of claim 1 wherein T 1 is greater than or equal to 2L, and wherein T 2 is greater than or equal to 2W.

18. A flexible printed circuit board (PCB), the PCB comprising:

a flexible substrate;

a plurality of row lines overlying the substrate, formed in a serpentine pattern with a plurality of partial-loops having chamfered corners;

a plurality of parallel column lines overlying the substrate, each column line formed in a serpentine pattern with a plurality of partial-loops having chamfered corners; and,

wherein the row line partial-loops orthogonally cross the column line partial-loops at their respective chamfered corners.

19. The PCB of claim 18 wherein the row line partial-loops have a 3-sided rectangular shape with an opening, with the openings of row-adjacent pixels 180 degrees out of phase; and,

wherein the column line partial-loops have a 3-sided rectangular shape, with the openings of column-adjacent pixels 180 degrees out of phase.

20. The PCB of claim 19 wherein the row line partial-loop openings of column-adjacent pixels are 180 degrees out of phase; and,

wherein the column line partial-loop openings of row-adjacent pixels are 180 degrees out of phase.

21. The PCB of claim 20 wherein a middle side of a row line partial-loop for a pixel in a (2n +1)th row and a (2m +2)th column, where n and m are integers greater than or equal to zero, is parallel to and adjacent a middle side of a row line for a pixel in a (2n +2)th row and the (2m +2)th column; and,

wherein a middle side of a column line partial-loop for a pixel in the (2n +1)th row and a (2m +1)th column, is parallel to and adjacent a middle side of a column line for a pixel in the (2n +1)th row and the (2m +2)th column.