IP Library › Granted Patent US 9,366,697
Granted Patent B2
US 9,366,697 · App. 13/699,255 · Granted Jun 14, 2016

Micromachined on-wafer probes and related method

Inventors: Robert M. Weikle, II (Crozet, VA); Arthur Weston Lichtenberger (Charlottesville, VA); Nicolas Scott Barker (Charlottesville, VA); Theodore James Reck (Charlottesville, VA); Haiyong Xu (Charlottesville, VA); Lihan Chen (Charlottesville, VA)
Assignee: University of Virginia Patent Foundation
G01R1/0416G01R1/067G01R1/06744G01R3/00
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Quick Facts
Patent No.
US 9,366,697
App. No.
13/699,255
Granted
Jun 14, 2016
Kind
B2
Abstract

A micromachining process to fabricate a single chip that simple drops into a supporting structure. The micromachining process provides the ability to create a probe that will interface with integrated circuits, for example, operating at frequencies in the range of about 100 GHz to about 3,000 GHz (3 THz). This approach creates a silicon structure (or other applicable choice of material) that provides mechanical force for probing while supporting the transfer of the high frequency energy between a measurement system and the integrated circuit, individual device or material.

Claims (50)

1. A device for probing a structure on a surface of an object substrate, said device comprising a compliant chip, wherein said compliant chip comprises a monolithic integrated circuit assembly comprising integrated electrical interconnects, said integrated electrical interconnects including:

at least one compliant beam oriented at a specified non-parallel angle with respect to said surface of said object substrate, said at least one compliant beam configured to electrically and mechanically probe said structure on said object substrate;

at least one transmission circuit; and

a waveguide transition element, wherein said at least one transmission circuit suitable to electrically interconnect said at least one compliant beam with said waveguide transition element.

2. The device of claim 1 , wherein said compliant chip is configured to be secured by a housing.

3. The device of claim 2 , wherein said compliant chip is configured to be secured by said housing including a detachable engagement of said compliant chip to said housing.

4. The device of claim 2 , wherein said securement is provided by compressive forces.

5. The device of claim 2 , wherein said housing comprises an aperture configured to receive said compliant chip.

6. The device of claim 5 , wherein said housing aperture comprises at least one of the following: slot, groove, recess, channel, tunnel, indentation, passage, split, or port.

7. The device of claim 2 , wherein said housing is configured to be re-usable when said compliant chip is detached and replaced with another compliant chip.

8. The device of claim 1 , wherein said integrated electrical interconnects of said compliant chip further comprises:

at least one of at least one bias current circuit or at least one bias voltage circuit, wherein said at least one bias current circuit or at least one bias voltage circuit is configured to electrically interconnect with said structure on said surface of said object substrate when said at least one compliant beam makes contact with said structure on said surface of said object substrate.

9. The device of claim 1 , wherein said compliant chip is configured to perform with direct current (DC) transmission.

10. The device of claim 1 , wherein when said compliant chip is pressed against said structure on a surface of said object substrate, the compliant chip makes electrical contact between said structure on said surface and said integrated electrical interconnects.

11. The device of claim 10 , where the pressing causes flexure in said compliant chip.

12. The device of claim 1 , wherein said at least one compliant beam comprises:

at least one contact tip, wherein said at least one contact tip electrically interconnected with said at least one compliant beam, and wherein said at least one contact tip configured to contact said structure on said surface of said object substrate when pressed against it.

13. The device of claim 12 , wherein said at least one contact tip configured to be compliant when said contact tip contacts the structure on a surface of an object substrate when pressed against it.

14. The device of claim 12 , wherein a plurality of said contact tips configured as a coplanar waveguide (CPW) in communication with said at least one transmission circuit.

15. The device of claim 1 , wherein said at least one compliant beam comprises:

a ground-signal (GS) circuit, wherein said ground-signal (GS) circuit electrically interconnected with said at least one transmission circuit, and wherein said at a ground-signal circuit (GS) configured to electrically interconnect with the structure on a surface of an object substrate when said at least one compliant beam is pressed against it.

16. The device of claim 1 , further comprising:

a secondary device for probing the structure on a surface of an object substrate, said secondary device comprising a secondary compliant chip, wherein said secondary compliant chip comprises a secondary monolithic integrated circuit assembly comprising secondary integrated electrical interconnects, and wherein said secondary compliant chip is configured to be secured by a secondary housing.

17. A device for probing a structure on a surface of an object substrate, said device comprising a compliant chip, wherein said compliant chip comprises a monolithic integrated circuit assembly comprising integrated electrical interconnects;

wherein said integrated electrical interconnects of said compliant chip comprise:

at least one compliant beam oriented at a specified non-parallel angle with respect to said surface of said object substrate;

at least one transmission circuit; and

a waveguide transition element, wherein said at least one transmission circuit suitable to electrically interconnect said at least one compliant beam with said waveguide transition element;

wherein said compliant chip is configured to be secured by a housing;

wherein when said compliant beam is pressed against said structure on said surface of said object substrate: (1) said pressing causes flexure in said compliant beam; and (2) said compliant beam makes electrical contact between said structure and said integrated electrical interconnects.

18. The device of claim 17 , wherein said integrated electrical interconnects of said compliant chip further comprise:

at least one of at least one bias current circuit or at least one bias voltage circuit, wherein said at least one bias current circuit or at least one bias voltage circuit is configured to electrically interconnect with the structure on a surface of an object substrate when said at least one compliant beam makes contact with said structure on a surface of an object substrate.

19. A method of testing a structure on a surface of an object substrate, wherein said testing method comprises:

electrically probing said surface of an object substrate using a device comprising a compliant chip, wherein said compliant chip comprises a monolithic integrated circuit assembly including integrated electrical interconnects; and

electrically interconnecting the device to a measurement instrument;

wherein said integrated electrical interconnects of said compliant chip comprise:

at least one compliant beam oriented at a specified non-parallel angle with respect to said surface of said object substrate;

at least one transmission circuit; and

a waveguide transition element, wherein said at least one transmission circuit suitable to electrically interconnect said at least one compliant beam with said waveguide transition element; and

wherein the electrically probing said surface of said object substrate comprises pressing said compliant beam against said structure on said surface of said object substrate, including (1) causing flexure in said compliant beam; and (2) establishing electrical contact between said structure and said integrated electrical interconnects using said compliant beam.

20. The method of claim 19 , wherein the surface on the object substrate comprises a sample of material with appropriate contacts or some other geometric feature that has been fabricated on the substrate surface.

21. The method of claim 19 , comprising securing said compliant chip using a housing.

22. The method of claim 21 , wherein said securement comprises detachably engaging said compliant chip to said housing.

23. The method of claim 22 , wherein said securement provided by compressive forces.

24. The method of claim 21 , wherein said housing comprises an aperture configured to receive said compliant chip.

25. The method of claim 24 , wherein said housing aperture comprises at least one of the following: slot, groove, recess, channel, tunnel, indentation, passage, split, or port.

26. The method of claim 21 , wherein said housing is configured to be re-usable when said compliant chip is detached and replaced with another compliant chip.

27. The method of claim 19 , wherein said integrated electrical interconnects of said compliant chip further comprise:

at least one of at least one bias current circuit or at least one bias voltage circuit, wherein said at least one bias current circuit or at least one bias voltage circuit is configured to electrically interconnect with the structure on a surface of an object substrate when said at least one compliant beam makes contact with said structure on a surface of an object substrate; and

wherein the method comprising biasing the structure on the surface of the object substrate using at least one of the bias current circuit or the bias voltage circuit.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE INVENTOR AND TO CORRECT THE EXECUTION DATE FOR ALL INVENTORS PREVIOUSLY RECORDED ON REEL 032841 FRAME 0814. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.. Recorded Jan 15, 2016
From: WEIKLE II, ROBERT M; LICHTENBERGER, ARTHUR W; BARKER, NICOLAS SCOTT; RECK, THEODORE J; XU, HAIYONG; CHEN, LIHAN
To: UNIVERSITY OF VIRGINIA
Reel/Frame 037540/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2014
From: WEIKLE, ROBERT M, II; LITCHENBERGER, ARTHUR W; BARKER, NICOLAS SCOTT; RECK, THEODORE J; XU, HAIYONG; CHEN, LIHAN
To: UNIVERSITY OF VIRGINIA
Reel/Frame 032841/0814 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2014
From: UNIVERSITY OF VIRGINIA
To: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
Reel/Frame 032841/0987 →
Continuity (3)
Provisional Application 61347013 · May 21, 2010
Provisional Application 61484004 · May 9, 2011
Related Publication 20130106456A1 · May 2, 2013