Event counter checkpointing and restoring
Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.
1. A method comprising:
storing, by a processor, prior to a transactional execution, a value of a first event counter employed to count events associated with the processor;
restoring the first event counter to the stored value after aborting the transactional execution;
causing the first event counter to resume counting events using the stored value as a base count; and
determining, in response to terminating the transactional execution, a number of events that occurred during the transactional execution, using the stored value of the first event counter, a current value of the first event counter, and a value of a second event counter employed to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is terminated.
2. The method of claim 1 , wherein the first event counter is to count events during the transactional execution.
3. The method of claim 1 , wherein the transactional execution comprises execution associated with a shared resource without locking the shared resource.
4. The method of claim 1 , wherein the transactional execution comprises execution within a transactional memory.
5. The method of claim 1 , wherein the event counter is to count the events associated with a type provided by at least one of: a cache reference, a cache miss, or a bus access.
6. The method of claim 1 , further comprising performing one of: enabling checkpointing of the first event counter or disabling checkpointing of the first event counter.
7. A non-transitory machine-readable storage medium to store instructions that, when executed by a processor cause the processor to:
store, prior to a transactional execution, a value of a first event counter programmed to count events associated with the processor;
restore the first event counter to the stored value after the transactional execution is terminated;
cause the first event counter to resume count events using the stored value as a base count; and
determine, in response to terminating the transactional execution, a number of events that occurred during the transactional execution, using the stored value of the first event counter, a current value of the first event counter, and a value of a second event counter employed to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is terminated.
8. The non-transitory machine-readable storage medium of claim 7 , wherein the transactional execution comprises execution associated with a shared resource without locking the shared resource.
9. The non-transitory machine-readable storage medium of claim 7 , wherein the transactional execution comprises execution within a transactional memory.
10. The non-transitory machine-readable storage medium of claim 7 , wherein the event counter is to count events associated with a type provided by at least one of: a cache reference, a cache miss, or a bus access.
11. The non-transitory machine-readable storage medium of claim 7 , further comprising executable instructions causing the processor to perform one of: enable checkpointing of the first event counter or disable checkpointing of the first event counter.
12. A processor comprising:
a first event counter to count events associated with the processor;
a second event counter to count events prior to and during a transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is terminated;
wherein the processor is to:
store, prior to the transactional execution, a value of the first event counter;
restore the first event counter to the stored value after the transactional execution is terminated,
cause the first event counter to resume counting events using the stored value as a base count, and
determine, in response to terminating the transactional execution, a number of events that occurred during the transactional execution, using the stored value of the first event counter, a current value of the first event counter, and a value of the second event counter.
13. The processor of claim 12 , wherein the transactional execution comprises execution associated with a shared resource without locking the shared resource.
14. The processor of claim 13 , wherein the processor allows concurrent access to the shared resource by multiple execution threads during the transactional execution.
15. The processor of claim 12 , wherein the transactional execution comprises execution within a transactional memory.
16. The processor of claim 12 , wherein the first event counter comprises a performance monitoring counter.
17. The processor of claim 12 , wherein the second event counter is to include events counted during a terminated transactional execution.
18. The processor of claim 12 , wherein the first event counter comprises a programmable event counter to count events of a particular type of a plurality of types.
19. The processor of claim 12 , wherein the event counter is to count events associated with a type provided by at least one of: a cache reference, a cache miss, or a bus access.
20. The processor of claim 12 , wherein the processor is further to perform one of: enable checkpointing of the first event counter or disable checkpointing of the first event counter.