Silicon carbide semiconductor device and method of manufacture thereof

1. A silicon carbide semiconductor device, comprising:

a first semiconductor layer having a first conductivity;

a second semiconductor layer located on the first semiconductor layer;

an insulation layer located on the second semiconductor layer;

a gate electrode located on the insulation layer;

a first doping zone having a second conductivity opposite to the first conductivity and a first doping boundary and being located in the first semiconductor layer along the second semiconductor layer;

a second doping zone having the first conductivity and a second doping boundary and being located in the first doping zone along the second semiconductor layer; and

a third doping zone having the second conductivity and being located in the first semiconductor layer along the second semiconductor layer and abutting the second doping zone and partially overlapped with the first doping zone;

wherein the first doping zone includes a channel control zone located along the second semiconductor layer between the first doping boundary and the second doping boundary;

wherein the channel control zone has impurity concentration distribution increased gradually from the first doping boundary to reach a maximum value between the first doping boundary and the second doping boundary, then decreased gradually toward the second doping boundary;

wherein the impurity concentration of the second semiconductor layer forms a gradient distribution in a thickness direction thereof;

wherein the gradient distribution has a peak value proximate the first semiconductor layer.

2. The silicon carbide semiconductor device of claim 1 , wherein the channel control zone is formed from the first doping boundary along the second semiconductor layer to the second doping boundary at a length ranged from 0.1 μm to 1 μm.

3. The silicon carbide semiconductor device of claim 1 , wherein the maximum impurity concentration of the channel control zone is ranged from 1×10 17 cm −3 to 1×10 20 cm −3 .

4. The silicon carbide semiconductor device of claim 1 , wherein the second semiconductor layer is formed at a thickness ranged from 0.01 μm to 0.5 μm.

5. The silicon carbide semiconductor device of claim 1 , wherein the impurity concentration of the second semiconductor layer is ranged from 1×10 15 cm −3 to 1×10 20 cm −3 .

6. The silicon carbide semiconductor device of claim 1 being arranged to form a metal oxide semiconductor field effect transistor.

7. The silicon carbide semiconductor device of claim 1 being arranged to form an insulated gate bipolar transistor.

8. The silicon carbide semiconductor device of claim 1 , wherein the silicon carbide semiconductor device has a threshold voltage greater than 1V.

9. A silicon carbide semiconductor device, comprising:

a first semiconductor layer having a first conductivity;

a second semiconductor layer located on the first semiconductor layer;

an insulation layer located on the second semiconductor layer;

a gate electrode located on the insulation layer;

a first doping zone having a second conductivity opposite to the first conductivity and a first doping boundary and being located in the first semiconductor layer along the second semiconductor layer;

a second doping zone having the first conductivity and a second doping boundary and being located in the first doping zone along the second semiconductor layer; and

a third doping zone having the second conductivity and being located in the first semiconductor layer along the second semiconductor layer and abutting the second doping zone and partially overlapped with the first doping zone;

wherein the first doping zone includes a channel control zone located along the second semiconductor layer between the first doping boundary and the second doping boundary;

wherein the channel control zone has impurity concentration distribution increased gradually from the first doping boundary to reach a maximum value between the first doping boundary and the second doping boundary, then decreased gradually toward the second doping boundary;

wherein the second semiconductor layer includes a plurality of epitaxy layers;

wherein the epitaxy layers include a first channel layer which has the first conductivity and a first impurity concentration and is located on the first semiconductor layer, and a second channel layer which has a second impurity concentration and is located on the first channel layer.

10. The silicon carbide semiconductor device of claim 9 , wherein the channel control zone is formed from the first doping boundary along the second semiconductor layer to the second doping boundary at a length ranged from 0.1 μm to 1 μm.

11. The silicon carbide semiconductor device of claim 9 , wherein the maximum impurity concentration of the channel control zone is ranged from 1×10 17 cm −3 to 1×10 20 cm −3 .

12. The silicon carbide semiconductor device of claim 9 , wherein the second semiconductor layer is formed at a thickness ranged from 0.01 μm to 0.5 μm.

13. The silicon carbide semiconductor device of claim 9 , wherein the second semiconductor layer has an impurity concentration ranged from 1×10 15 cm −3 to 1×10 20 cm −3 .

14. The silicon carbide semiconductor device of claim 9 , wherein the first impurity concentration is higher than the second impurity concentration.

15. The silicon carbide semiconductor device of claim 9 , wherein the second channel layer has the first conductivity.

16. The silicon carbide semiconductor device of claim 9 , wherein the second channel layer has the second conductivity.

17. The silicon carbide semiconductor device of claim 9 , being arranged to form a metal oxide semiconductor field effect transistor.

18. The silicon carbide semiconductor device of claim 9 being arranged to form an insulated gate bipolar transistor.

19. The silicon carbide semiconductor device of claim 9 , wherein the silicon carbide semiconductor device has a threshold voltage greater than 1V.