Static random access memory
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.
1. A static random access memory (SRAM), comprising:
a plurality of SRAM cells on a substrate, wherein each of the SRAM cells comprises:
a gate structure on the substrate;
at least one fin-shaped structure disposed on the substrate, wherein the arrangement direction of the fin-shaped structure is perpendicular to the arrangement direction of the gate structure;
a first interlayer dielectric (ILD) layer around the gate structure;
a first contact plug in the first ILD layer, wherein the first contact plug is a strip-shaped structure, and directly contacts two fin-shaped structures; and
a second ILD layer on the first ILD layer.
2. The SRAM of claim 1 , wherein each of the SRAM cells comprises a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor and a second access transistor.
3. The SRAM of claim 2 , wherein the first contact plug is electrically connected to a drain of the first pull-up transistor, a drain of the first pull-down transistor and a drain of the first access transistor.
4. The SRAM of claim 2 , wherein the first contact plug is electrically connected to a drain of the second pull-up transistor, a drain of the second pull-down transistor and a drain of the second access transistor.
5. The SRAM of claim 2 , further comprising a second contact plug, wherein the second contact plug is electrically connected to a drain of the second pull-up transistor and a gate of the first pull-up transistor.
6. The SRAM of claim 5 , wherein the second contact plug is disposed within the second ILD layer.
7. The SRAM of claim 5 , wherein the second contact plug is disposed within the first ILD layer.
8. The SRAM of claim 7 , wherein the second contact plug and the first contact plug are a monolithically formed structure, and the second contact plug directly contacts the first contact plug.
9. The SRAM of claim 5 , wherein the extending direction of the second contact plug is parallel to the arrangement direction of each fin-shaped structure.
10. The SRAM of claim 2 , further comprising at least two word lines, electrically connected to a gate of the first access transistor and a gate of the second access transistor.
11. The SRAM of claim 2 , further comprising at least two bit lines, electrically connected to a source of the first access transistor and a source of the second access transistor.
12. The SRAM of claim 2 , further comprising at least two voltage sources (Vss), electrically connected to a source of the first pull-down transistor and a source of the second pull-down transistor.
13. The SRAM of claim 2 , further comprising at least two voltage sources (Vcc), electrically connected to a source of the first pull-up transistor and a source of the second pull-up transistor.
14. The SRAM of claim 1 , further comprising a stop layer disposed between the first ILD layer and the second ILD layer.
15. The SRAM of claim 1 , wherein the extending direction of the first contact plug is perpendicular to the arrangement direction of each fin-shaped structure.
16. The SRAM of claim 1 , further comprising a third ILD layer disposed on the second ILD layer.
17. The SRAM of claim 16 , further comprising at least one third contact plug, at least disposed within the third ILD, and electrically connected to a bottom plug of the SRAM cell.
18. The SRAM of claim 17 , wherein the third contact plug is disposed within the third ILD layer and within the second ILD layer.