Imaging device with drive voltage dependent on external light intensity
View Patent ↗A solid-state imaging device increases the SN ratio of a signal even when external light intensity is low. The solid-state imaging device includes a sensor circuit that includes a light-receiving element, a first transistor that controls connection between a first wiring and a node in which the amount of accumulated charge is determined by the amount of exposure to the light-receiving element, a second transistor whose on or off state is selected in accordance with the potential of the node, and a third transistor that controls connection between a second wiring and a third wiring together with the second transistor; a central processing unit that selects a first driving method or a second driving method in accordance with external light intensity; and a controller that controls a potential supplied to the gate of the first transistor in accordance with the first driving method or the second driving method.
1. A semiconductor device comprising:
a light-receiving element;
a first transistor;
a second transistor;
a third transistor;
a CPU; and
a controller,
wherein one of electrodes of the light-receiving element is electrically connected to a node,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the node,
wherein a gate of the second transistor is electrically connected to the node,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a wiring,
wherein the wiring is electrically connected to the CPU,
wherein the CPU is electrically connected to the controller,
wherein the controller is electrically connected to a gate of the first transistor,
wherein the first transistor comprises an oxide semiconductor layer in a channel formation region,
wherein an oxide layer containing oxygen at a proportion higher than a stoichiometric composition is located over the source electrode, the drain electrode and the oxide semiconductor layer,
wherein the CPU is configured to select a first driving method in which a third potential which is higher than a first potential and lower than a second potential is supplied to the gate of the first transistor in accordance with an external light intensity,
wherein the controller is configured to supply the third potential to the gate of the first transistor in accordance with a result of a selection of the CPU,
wherein the first potential makes the first transistor be in an off state, and
wherein the second potential makes the first transistor be in an on state.
2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.
3. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises a crystal region, and
wherein c-axes of the crystal region are aligned in a direction substantially perpendicular to a bottom surface or a top surface of the oxide semiconductor layer.
4. The semiconductor device according to claim 1 , wherein the second transistor comprises silicon in a channel formation region.
5. An imaging device comprising:
a sensor circuit comprising:
a light-receiving element;
a first transistor;
a second transistor; and
a third transistor;
a CPU; and
a circuit,
wherein one of electrodes of the light-receiving element is electrically connected to a node,
wherein the first transistor is electrically connected between a first wiring and the node,
wherein a gate of the second transistor is electrically connected to the node,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to and a third wiring,
wherein the third wiring is electrically connected to the CPU,
wherein the CPU is electrically connected to the circuit,
wherein the circuit is electrically connected to a gate of the first transistor,
wherein the CPU is configured to select a first driving method in which a third potential which is higher than a first potential and lower than a second potential is supplied to the gate of the first transistor in accordance with an external light intensity,
wherein the circuit is configured to supply the third potential to the gate of the first transistor in accordance with a result of a selection of the CPU,
wherein the first potential makes the first transistor be in an off state, and
wherein the second potential makes the first transistor be in an on state.
6. The imaging device according to claim 5 , wherein the first transistor comprises an oxide semiconductor layer in a channel formation region.
7. The imaging device according to claim 6 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.
8. The imaging device according to claim 6 ,
wherein the oxide semiconductor layer comprises a crystal region, and
wherein c-axes of the crystal region are aligned in a direction substantially perpendicular to a bottom surface or a top surface of the oxide semiconductor layer.
9. The imaging device according to claim 6 ,
wherein the first transistor includes a pair of gates which is electrically connected to each other and overlaps each other with the oxide semiconductor layer interposed therebetween, and
wherein an end portion of the oxide semiconductor layer in a channel width direction overlaps the pair of gates.
10. A semiconductor display device comprising:
a light-emitting element;
a sensor circuit comprising:
a light-receiving element;
a first transistor;
a second transistor; and
a third transistor;
a CPU; and
a circuit,
wherein one of electrodes of the light-receiving element is electrically connected to a node,
wherein the first transistor is electrically connected between a first wiring and the node,
wherein a gate of the second transistor is electrically connected to the node,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to and a third wiring,
wherein the third wiring is electrically connected to the CPU,
wherein the CPU is electrically connected to the circuit,
wherein the circuit is electrically connected to a gate of the first transistor,
wherein the CPU is configured to select a first driving method in which a third potential which is higher than a first potential and lower than a second potential is supplied to the gate of the first transistor in accordance with an external light intensity,
wherein the circuit is configured to supply the third potential to the gate of the first transistor in accordance with a result of a selection of the CPU,
wherein the first potential makes the first transistor be in an off state,
wherein the second potential makes the first transistor be in an on state, and
wherein luminance of the light-emitting element is controlled by an image signal.
11. The semiconductor display device according to claim 10 , wherein the first transistor comprises an oxide semiconductor layer in a channel formation region.
12. The semiconductor display device according to claim 11 , wherein the oxide semiconductor layer comprises In, Ga, and Zn.
13. The semiconductor display device according to claim 11 ,
wherein the oxide semiconductor layer comprises a crystal region, and
wherein c-axes of the crystal region are aligned in a direction substantially perpendicular to a bottom surface or a top surface of the oxide semiconductor layer.
14. The semiconductor display device according to claim 11 ,
wherein the first transistor includes a pair of gates which is electrically connected to each other and overlaps each other with the oxide semiconductor layer positioned therebetween, and
wherein an end portion of the oxide semiconductor layer in a channel width direction overlaps the pair of gates.