Gate driver circuit and display apparatus having the same
This disclosure provides a gate driver circuit in a display. The gate driver circuit includes shift registers configured for receiving clock and start signals and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a panel, each register comprising: a control unit having a clock input, a first voltage input, a second voltage input, and a first output; and a first output unit having a first pull-down TFT electrically connected to one of the first outputs and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input is provided to the first output unit; and a first control signal's period at the first output is longer than the clock signal's period at the clock input and shorter than the period of a frame.
1. A gate driver circuit having a plurality of shift registers, each of the shift registers configured for receiving at least one clock signal and a start signal and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a display panel, the shift register comprising:
a control unit having at least one clock input terminal, a first voltage input terminal, a second voltage input terminal, and at least one first output terminal; and
a first output unit having a first pull-down TFT electrically connected to one of the first output terminals and a gate-driving terminal configured for providing the gate signal;
wherein one of the clock signals at the clock input terminal is provided to the first output unit;
wherein a first control signal's period at the first output terminal is longer than the clock signal's period at the clock input terminal and shorter than the period of a frame; and
wherein the control unit further comprises a second output terminal and a second output unit having a second pull-down TFT electrically connected to the second output terminal and the gate-driving terminal; the other one of the clock signal at the clock input terminal is provided to the second output unit, and a second control signal's period at the second output terminal is longer than the clock signal's period selected at the clock input terminal and shorter than the period of a frame.
2. The gate driver circuit according to claim 1 , wherein the first voltage input terminal receives a first voltage signal, the second voltage input terminal receives a second voltage signal, and the voltage signals are processed by the control unit to produce the control signals to control the first and second output terminals, which further control ON-state and OFF-state durations of the first and second pull-down TFTs.
3. The gate driver circuit according to claim 1 , wherein the first control signal's period at the first output terminal is equal to the second control signal's period at the second output terminal.
4. A display apparatus comprising a panel having a gate driver circuit, the gate driver circuit comprising a plurality of shift registers, each of the shift registers configured for receiving at least one clock signal and a start signal and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on the panel, the shift register comprising:
a control unit having at least one clock input terminal, a first voltage input terminal, a second voltage input terminal, and at least one first output terminal; and
a first output unit having a first pull-down TFT electrically connected to one of the first output terminals and a gate-driving terminal configured for providing the gate signal;
wherein one of the clock signals at the clock input terminal is provided to the first output unit;
wherein a first control signal's period at the first output terminal is longer than the clock signal's period at the clock input terminal and shorter than the period of a frame; and
wherein the control unit further comprises a second output terminal and a second output unit having a second pull-down TFT electrically connected to the second output terminal and the gate-driving terminal; the other one of the clock signal at the clock input terminal is provided to the second output unit, and a second control signal's period selected at the clock input terminal at the second output terminal is longer than the clock signal's period and shorter than the period of a frame.
5. The display apparatus according to claim 4 , wherein the first voltage input terminal receives a first voltage signal, the second voltage input terminal receives a second voltage signal, and the voltage signals are processed by the control unit to produce the control signals to control the first and second output terminals, which further control ON-state and OFF-state durations of the first and second pull-down TFTs.
6. The display apparatus according to claim 4 , wherein the first control signal's period at the first output terminal is equal to the second control signal's period at the second output terminal.
7. A display device comprising:
a pixel portion including a plurality of pixels, arranged at intersections of the gate lines and the data lines on a display panel; and
a gate driver circuit electrically connected to the pixel portion and having a plurality of shift registers,
wherein the shift registers configured for receiving at least one clock signal and a start signal and generating a gate signal to drive a row of the pixels:
wherein the shift register comprising:
a control unit having at least one clock input terminal, a first voltage input terminal, a second voltage input terminal, and at least one first output terminal, and one of the clock signals at the clock input terminal is provided to the first output unit; and
a first output unit having at least one pull-down TFT electrically connected to one of the first output terminals and a gate-driving terminal configured for providing the gate signal;
wherein the control signal of the pull-down TFT extending its HIGH-state duration and HIGH-state duration is longer than the clock signal's period at clock input terminal; and
wherein the control unit further comprises a second output terminal and a second output unit having a second pull-down TFT electrically connected to the second output terminal and the gate-driving terminal; the other one of the clock signal at the clock input terminal is provided to the second output unit, and a second control signal's period selected at the clock input terminal at the second output terminal is longer than the clock signal's period and shorter than the period of a frame.
8. The display apparatus according to claim 7 , wherein the first voltage input terminal receives a first voltage signal, the second voltage input terminal receives a second voltage signal, and the voltage signals are processed by the control unit to produce the control signals to control the first and second output terminals, which further control ON-state and OFF-state durations of the first and second pull-down TFTs.
9. The display apparatus according to claim 7 , wherein the first control signal's period at the first output terminal is equal to the second control signal's period at the second output terminal.
10. The display apparatus according to claim 7 , wherein a first control signal's period at the first output terminal is longer than the clock signal's period at the clock input terminal.
11. The display apparatus according to claim 7 , wherein the first control signal's period at the first output terminal is shorter than the period of a frame.