Electronic device and method for fabricating the same
An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first planes and a plurality of second planes which are disposed over a substrate and alternately stacked in a vertical direction over the substrate, where each of the first planes includes a plurality of first lines which extends in a first direction parallel to the substrate and each of the second planes includes a plurality of second lines which extends in a second direction parallel to the substrate and intersecting with the first direction, a plurality of variable resistance patterns which is interposed between each of the first planes and each of the second planes, each of the variable resistance patterns being disposed at a cross point between a first line and a corresponding second lines, and an air-gap which is disposed between neighboring variable resistance patterns.
1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising:
one or more first planes and one or more second planes, the first and second planes being alternately stacked in a vertical direction over the substrate, each of the first planes including a plurality of first lines extending in a first horizontal direction, each of the second planes including a plurality of second lines extending in a second horizontal direction, the second horizontal direction intersecting with the first horizontal direction;
a plurality of variable resistance patterns interposed between each of the first planes and a corresponding one of the second planes, each of the variable resistance patterns being disposed at a cross point between a first line and a corresponding second line; and
an air-gap disposed between neighboring variable resistance patterns that are at substantially the same level in the vertical direction,
wherein the air-gap extends in the vertical direction to penetrate through the first and second planes in a region enclosed by two neighboring first lines and corresponding two neighboring second lines.
2. The electronic device according to claim 1 , further comprising an insulating pattern surrounding the plurality of variable resistance patterns that are at substantially the same level in the vertical direction.
3. The electronic device according to claim 2 , wherein the insulating pattern includes a mesh-like structure and surrounds the air-gap.
4. The electronic device according to claim 2 , wherein the plurality of variable resistance patterns include a first metal oxide having oxygen vacancies, and the insulating pattern includes a second metal oxide, the second metal oxide having a greater oxygen content than the first metal oxide.
5. The electronic device according to claim 4 , wherein the second metal oxide satisfies a stoichiometric ratio.
6. The electronic device according to claim 1 , further comprising a plurality of insulating patterns which have an island shape, each of the plurality of insulating patterns surrounding each of the variable resistance patterns,
wherein the air-gap includes a mesh-like structure and surrounds the plurality of insulating patterns.
7. The electronic device according to claim 1 , wherein the air-gap includes a mesh-like structure and surrounds the variable resistance patterns.
8. The electronic device according to claim 1 , wherein each of the plurality of variable resistance patterns has a tetragon shape including four curved line segments such that two diagonals of said each of the plurality of variable resistance patterns are substantially parallel to the first horizontal direction and the second horizontal direction, respectively.
9. The electronic device according to claim 1 , further comprising:
first spacers disposed on both sidewalls of each of the plurality of first lines; and
second spacers disposed on both sidewalls of each of the plurality of second lines,
wherein the air-gap is disposed between neighboring first spacers and between neighboring second spacers.
10. The electronic device according to claim 9 , further comprising:
a first insulating pattern which is disposed in a space between two neighboring first lines in the same plane; and
a second insulating pattern which is disposed in a space between two neighboring second lines in the same plane,
wherein the air-gap penetrates through the first and second insulating patterns.
11. The electronic device according to claim 10 , wherein the first and second spacers include a material having an etch rate lower than that of the first and second insulating patterns and the variable resistance patterns.
12. The electronic device according to claim 1 , further comprising:
a first insulating pattern disposed in a space between two neighboring first lines in the same plane; and
a second insulating pattern disposed in a space between two neighboring second lines in the same plane,
wherein the air-gap penetrates through the first and second insulating patterns.
13. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory unit is a part of the memory unit in the microprocessor.
14. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory unit is a part of the cache memory unit in the processor.
15. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory unit is a part of the auxiliary memory device or the main memory device in the processing system.
16. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory unit is a part of the storage device or the temporary storage device in the data storage system.
17. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory unit is a part of the memory or the buffer memory in the memory system.