Pipelined programmable feed forward equalizer (FFE) for a receiver
View Patent ↗A programmable feed forward equalizer (FFE) includes a plurality of unit cells, each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch. The FFE also comprises clock logic configured to control the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element, the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.
1. A receiver, comprising:
a programmable feed forward equalizer (FFE) that receives an input signal from a linear equalizer, comprising:
a plurality of unit cells, each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch;
clock logic configured to control the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element; and
the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.
2. The programmable FFE of claim 1 , wherein a value of the filter coefficient is determined by one or more of a value of the capacitive element, enabling one or more of the plurality of unit cells, and determining a sign of the filter coefficient.
3. The programmable FFE of claim 1 , wherein the clock logic determines the selected voltage signal by selecting a subset of eight phases of a clock signal and a phase of the selected voltage signal determines the voltage applied to the capacitive element.
4. The programmable FFE of claim 1 , wherein the capacitive element comprises two capacitive elements configured to process a differential signal.
5. The programmable FFE of claim 1 , wherein a first input sample is provided to a first unit cell and a second input sample is provided to a second unit cell, the first input sample offset from the second input sample by one unit interval of a system clock.
6. The programmable FFE of claim 5 , wherein the first input sample is held in the first unit cell while the second input is provided to the second unit cell.
7. The programmable FFE of claim 1 , wherein a first input sample is provided to a first unit cell and a second input sample is provided to a second unit cell, the first input sample offset from the second input sample by one unit interval of a system clock, wherein the first input sample is held in the first unit cell while the second input is provided to the second unit cell, and wherein the clock logic determines the selected voltage signal by selecting a subset of eight phases of a clock signal and a phase of the selected voltage signal determines the voltage applied to the capacitive element.
8. A method, comprising:
providing an input signal to a plurality of unit cells belonging to a programmable feed forward equalizer (FFE), each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch;
controlling the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element; and
causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.
9. The method of claim 8 , further comprising determining a value of the filter coefficient by one or more of selecting a value of the capacitive element, enabling one or more of the plurality of unit cells, and determining a sign of the filter coefficient.
10. The method of claim 8 , further comprising determining the selected voltage signal by selecting a subset of eight phases of a clock signal and a phase of the selected voltage signal determines the voltage applied to the capacitive element.
11. The method of claim 8 , wherein the capacitive element comprises two capacitive elements configured to process a differential signal.
12. The method of claim 8 , further comprising:
providing a first input sample to a first unit cell and providing a second input sample to a second unit cell, the first input sample offset from the second input sample by one unit interval of a system clock.
13. The method of claim 12 , further comprising holding the first input sample in the first unit cell while the second input is provided to the second unit cell.
14. A receiver, comprising:
a linear equalizer configured to develop an input signal for a feed forward equalizer (FFE);
the FFE comprising:
a plurality of unit cells, each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch;
clock logic configured to control the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element; and
the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.
15. The receiver of claim 14 , wherein a value of the filter coefficient is determined by one or more of a value of the capacitive element, enabling one or more of the plurality of unit cells, and determining a sign of the filter coefficient.
16. The receiver of claim 14 , wherein the clock logic determines the selected voltage signal by selecting a subset of eight phases of a clock signal and a phase of the selected voltage signal determines the voltage applied to the capacitive element.
17. The receiver of claim 14 , wherein the capacitive element comprises two capacitive elements configured to process a differential signal.
18. The receiver of claim 14 , wherein a first input sample is provided to a first unit cell and a second input sample is provided to a second unit cell, the first input sample offset from the second input sample by one unit interval of a system clock.
19. The receiver of claim 18 , wherein the first input sample is held in the first unit cell while the second input is provided to the second unit cell.
20. The receiver of claim 14 , wherein the clock logic determines the selected voltage signal by selecting a subset of eight phases of a clock signal and a phase of the selected voltage signal determines the voltage applied to the capacitive element, wherein a first input sample is provided to a first unit cell and a second input sample is provided to a second unit cell, the first input sample offset from the second input sample by one unit interval of a system clock, and wherein the first input sample is held in the first unit cell while the second input is provided to the second unit cell.