IP Library › Granted Patent US 9,389,064
Granted Patent B2
US 9,389,064 · App. 14/229,446 · Granted Jul 12, 2016

Inline inspection of the contact between conductive traces and substrate for hidden defects using white light interferometer with tilted objective lens

Inventors: Shuhong Liu (Chandler, AZ); Zhiyong Wang (Chandler, AZ); Nilanjan Ghosh (Chandler, AZ); Deepak Goyal (Phoenix, AZ)
Assignee: Intel Corporation
G01B9/0203G01B9/0209G01B11/0675G01N21/956G02B21/0016G01B2210/56
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Quick Facts
Patent No.
US 9,389,064
App. No.
14/229,446
Granted
Jul 12, 2016
Kind
B2
Abstract

Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line monitoring of both resist footing defects and conductive trace undercut defects. The defects may be detected at the interface between dry film resist (DFR) footings and conductive trace footing formed on insulating layer top surfaces of a packaging substrate. Such footing and undercut defects may other wise be considered “hidden defects”. Using the WLI microscope with a tilted objective lens provides a high-throughput and low cost metrology and tool for non-destructive, non-contact, in-line monitoring.

Claims (21)

1. A method for detecting defects in an interface between conductive traces and an insulating substrate surface, the method comprising:

forming dry film resist (DFR) islands on the insulating substrate surface;

tilting an object lens of a white light interferometer (WLI) microscope to put an axis of the object lens at a first inspection angle of between 2 and 20 degrees with respect to a tangent of the insulating substrate surface; and

inspecting the insulating substrate surface and side surfaces of the DFR islands for DFR footing defects using the tilted object lens at the first inspection angle.

2. The method of claim 1 , wherein inspecting the insulating substrate surface and side surfaces of the DFR islands includes moving the insulating substrate surface with respect to the object lens, in a direction across the side surfaces of the DFR islands.

3. The method of claim 1 , further comprising, after inspecting for DFR footing defects:

plating conductor between the DFR islands and etching to remove the DFR islands to form conductor traces from the plated conductor;

tilting an object lens of a white light interferometer (WLI) microscope to put an axis of the object lens at a second inspection angle of between 5 and 20 degrees with respect to a tangent of the insulating substrate surface; and

inspecting the insulating substrate surface and side surfaces of the traces for conductor trace undercut (CTU) defects using the tilted object lens at the second inspection angle.

4. The method of claim 3 , wherein inspecting the insulating substrate surface and side surfaces of the traces includes moving the insulating substrate surface with respect to the object lens, in a direction across the side surfaces of the traces.

5. The method of claim 3 , wherein tilting the object lens at the first inspection angle comprises one of tilting the entire microscope or tiling only the object lens of the microscope; and

wherein tilting the object lens at the second inspection angle comprises (1) one of tilting the entire microscope or tilting only the object lens of the microscope, and (2) tilting the insulating substrate surface.

6. The method of claim 3 , wherein tilting to inspect for DFR footing defects includes tilting to put an axis of the object lens at an angle between 2 and 5 degrees with respect to a tangent of the insulating substrate surface; and

wherein tilting to inspect for CTU defects includes tilting to put an axis of the object lens at an angle of between 5 and 10 degrees with respect to a tangent of the insulating substrate surface.

7. The method of claim 3 , wherein inspecting for DFR footing defects occurs during in-line formation of a processor package including the insulating substrate surface, occurs after forming the DFR islands, and occurs prior to plating conductor between the islands; and

wherein inspecting for CTU defects occurs during in-line formation of a processor package including the insulating substrate surface, occurs after formation of the conductive traces, and occurs prior to forming material over the conductor traces.

8. The method of claim 3 , wherein inspecting for DFR footing or CTU defects includes creating a three-dimensional X,Y surface profile image having a Z resolution between 1 and 2 nanometers (nm) of the insulating substrate surface and DFR island sidewalls or conductor trace sidewalls.

9. The method of claim 1 , wherein inspecting for DFR footing defects or CTU defects includes imaging at a Z-resolution capable of imaging one of a DFR footing defect or a CTU defect having a height of between 200 nm and 2 microns; and a width of between 200 nm and 2 microns.

10. The method of claim 1 , wherein inspecting for DFR footing defects includes rotating one of (1) the insulating substrate surface or (2) the WLI, with respect to the Z axis of the insulating substrate surface, by an angle of one of 90 degrees, 180 degrees or 270 degrees.

11. The method of claim 1 , wherein the insulating substrate surface is part of a substrate package upon which a microprocessor can be mounted or bonded.

12. The method of claim 1 , wherein inspecting inspect for DFR footing defects includes inspecting during in-line formation using a line by line fan beam scan performed by the WLI.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2014
From: LIU, SHUHONG; WANG, ZHIYONG; GHOSH, NILANJAN Z.; GOYAL, DEEPAK
To: INTEL CORPORATION
Reel/Frame 033081/0869 →
Continuity (1)
Related Publication 20150276375A1 · Oct 1, 2015